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Home > ARM and Thumb Instructions > Parallel add and subtract |

Various byte-wise and halfword-wise additions and subtractions.

<>`prefix`

{`op`

} {`cond`

},`Rd`

,`Rn`

`Rm`

where:

`<`

>`prefix`

is one of:

`S`

Signed arithmetic modulo 2

^{8}or 2^{16}. Sets APSR GE flags.`Q`

Signed saturating arithmetic.

`SH`

Signed arithmetic, halving the results.

`U`

Unsigned arithmetic modulo 2

^{8}or 2^{16}. Sets APSR GE flags.`UQ`

Unsigned saturating arithmetic.

`UH`

Unsigned arithmetic, halving the results.

`op`

is one of:

`ADD8`

Byte-wise Addition

`ADD16`

Halfword-wise Addition.

`SUB8`

Byte-wise Subtraction.

`SUB16`

Halfword-wise Subtraction.

`ASX`

Exchange halfwords of

, then Add top halfwords and Subtract bottom halfwords.`Rm`

`SAX`

Exchange halfwords of

, then Subtract top halfwords and Add bottom halfwords.`Rm`

`cond`

is an optional condition code.

`Rd`

is the destination register.

`Rm, Rn`

are the ARM registers holding the operands.

These instructions perform arithmetic operations separately on the bytes or halfwords of the operands. They perform two or four additions or subtractions, or one addition and one subtraction.

You can choose various kinds of arithmetic:

Signed or unsigned arithmetic modulo 2

^{8}or 2^{16}. This sets the APSR GE flags.Signed saturating arithmetic to one of the signed ranges -2

^{15}≤≤ 2`x`

^{15}-1 or -2^{7}≤≤ 2`x`

^{7}-1. The Q flag is not affected even if these operations saturate.Unsigned saturating arithmetic to one of the unsigned ranges 0 ≤

≤ 2`x`

^{16}-1 or 0 ≤≤ 2`x`

^{8}-1. The Q flag is not affected even if these operations saturate.Signed or unsigned arithmetic, halving the results. This cannot cause overflow.

You cannot use PC for any register.

You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

These instructions do not affect the N, Z, C, V, or Q flags.

The `Q`

, `SH`

, `UQ`

and `UH`

prefix
variants of these instructions do not change the flags.

The `S`

and `U`

prefix variants
of these instructions set the GE flags in the APSR as follows:

For byte-wise operations, the GE flags are used in the same way as the C (Carry) flag for 32-bit

`SUB`

and`ADD`

instructions:`GE[0]`

for bits[7:0] of the result

`GE[1]`

for bits[15:8] of the result

`GE[2]`

for bits[23:16] of the result

`GE[3]`

for bits[31:24] of the result.

For halfword-wise operations, the GE flags are used in the same way as the C (Carry) flag for normal word-wise

`SUB`

and`ADD`

instructions:`GE[1:0]`

for bits[15:0] of the result

`GE[3:2]`

for bits[31:16] of the result.

You can use these flags to control a following `SEL`

instruction.

For halfword-wise operations, GE[1:0] are set or cleared together, and GE[3:2] are set or cleared together.

These ARM instructions are available in ARMv6 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.

There are no 16-bit Thumb versions of these instructions.

QHADD r2, r9, r3 ; No such instruction, should be QHADD8 or QHADD16 SAX r10, r8, r5 ; Must have a prefix.

- Reference