ARM® Compiler toolchain v5.02 for µVision Assembler Reference


List of Topics

Conventions and feedback
Assembler command line options
Assembler command line syntax
Assembler command line options
--16
--32
--apcs=qualifier…qualifier
--arm
--arm_only
--bi
--bigend
--brief_diagnostics
--checkreglist
--compatible=name
--cpreproc
--cpreproc_opts=options
--cpu=list
--cpu=name
--debug
--depend=dependfile
--depend_format=string
--diag_error=tag{, tag}
--diag_remark=tag{, tag}
--diag_style=style
--diag_suppress=tag{, tag}
--diag_warning=tag{, tag}
--dllexport_all
--dwarf2
--dwarf3
--errors=errorfile
--execstack
--exceptions
--exceptions_unwind
--fpmode=model
--fpu=list
--fpu=name
-g
--help
-idir{,dir, …}
--keep
--length=n
--li
--library_type=lib
--licretry
--list=file
--list=
--littleend
-m
--maxcache=n
--md
--no_code_gen
--no_esc
--no_execstack
--no_exceptions
--no_exceptions_unwind
--no_hide_all
--no_reduce_paths
--no_regs
--no_terse
--no_unaligned_access
--no_warn
-o filename
--pd
--predefine "directive"
--reduce_paths
--regnames=none
--regnames=callstd
--regnames=all
--report-if-not-wysiwyg
--show_cmdline
--split_ldm
--thumb
--thumbx
--unaligned_access
--unsafe
--untyped_local_labels
--version_number
--via=file
--vsn
--width=n
--xref
ARM and Thumb Instructions
Instruction summary
Instruction width specifiers
Memory access instructions
General data processing instructions
Flexible second operand (Operand2)
Operand2 as a constant
Operand2 as a register with optional shift
Shift operations
Multiply instructions
Saturating instructions
Parallel instructions
Parallel add and subtract
Packing and unpacking instructions
Branch and control instructions
Coprocessor instructions
Miscellaneous instructions
ThumbEE instructions
Pseudo-instructions
Condition codes
ADD, SUB, RSB, ADC, SBC, and RSC
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND, ORR, EOR, BIC, and ORN
ASR, LSL, LSR, ROR, and RRX
B, BL, BX, BLX, and BXJ
BFC and BFI
BKPT
CBZ and CBNZ
CDP and CDP2
CHKA
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB, DSB, and ISB
ENTERX and LEAVEX
ERET
HB, HBL, HBLP, and HBP
IT
LDC, LDC2, STC, and STC2
LDM and STM
LDR and STR (immediate offset)
LDR and STR (register offset)
LDR and STR, unprivileged
LDR (PC-relative)
LDR (register-relative)
LDR pseudo-instruction
LDREX and STREX
MAR and MRA
MCR, MCR2, MCRR, and MCRR2
MIA, MIAPH, and MIAxy
MOV and MVN
MOV32 pseudo--instruction
MOVT
MRC, MRC2, MRRC and MRRC2
MRS (system coprocessor register to ARM register)
MRS (PSR to general-purpose register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL, MLA, and MLS
NEG pseudo-instruction
PKHBT and PKHTB
PLD, PLDW, and PLI
PUSH and POP
QADD, QSUB, QDADD, and QDSUB
REV, REV16, REVSH, and RBIT
RFE
SBFX and UBFX
SDIV and UDIV
SEL
SETEND
SEV, WFE, WFI, and YIELD
SMC
NOP
SMLAD and SMLSD
SMLALxy
SMLALD and SMLSLD
SMMUL, SMMLA, and SMMLS
SMUAD{X} and SMUSD{X}
SMULxy and SMLAxy
SMULWy and SMLAWy
SRS
SSAT and USAT
SSAT16 and USAT16
SUBS pc, lr
SVC
SWP and SWPB
SXT, SXTA, UXT, and UXTA
SYS
TBB and TBH
TST and TEQ
UMULL, UMLAL, SMULL, and SMLAL
UMAAL
UND pseudo-instruction
USAD8 and USADA8
VFP Programming
VFP instruction summary
VFP pseudo-instructions
VFP instructions
VABS, VNEG, and VSQRT
VADD, VSUB, and VDIV
VCMP
VCVT (between single-precision and double-precision)
VCVT (between floating-point and integer)
VCVT (between floating-point and fixed-point)
VCVTB, VCVTT (half-precision extension)
VLDM, VSTM, VPOP, and VPUSH
VLDR and VSTR
VLDR pseudo-instruction
VLDR and VSTR (post-increment and pre-decrement)
VFMA, VFMS, VFNMA, VFNMS
VMOV
VMOV (between two ARM registers and an extension register)
VMOV (between one ARM register and single precision VFP)
VMRS and VMSR
VMUL, VMLA, VMLS, VNMUL, VNMLA, and VNMLS
Directives Reference
Alphabetical list of directives
Symbol definition directives
Data definition directives
About assembly control directives
About frame directives
Reporting directives
Instruction set and syntax selection directives
Miscellaneous directives
ALIAS
ALIGN
AREA
ARM, THUMB, THUMBX, CODE16 and CODE32
ASSERT
ATTR
CN
COMMON
CP
DATA
DCB
DCD and DCDU
DCDO
DCFD and DCFDU
DCFS and DCFSU
DCI
DCQ and DCQU
DCW and DCWU
DN, and SN
END
ENDFUNC or ENDP
ENTRY
EQU
EXPORT or GLOBAL
EXPORTAS
FIELD
FRAME ADDRESS
FRAME POP
FRAME PUSH
FRAME REGISTER
FRAME RESTORE
FRAME RETURN ADDRESS
FRAME SAVE
FRAME STATE REMEMBER
FRAME STATE RESTORE
FRAME UNWIND ON
FRAME UNWIND OFF
FUNCTION or PROC
GBLA, GBLL, and GBLS
GET or INCLUDE
IF, ELSE, ENDIF, and ELIF
IMPORT and EXTERN
INCBIN
INFO
KEEP
LCLA, LCLL, and LCLS
LTORG
MACRO and MEND
MAP
MEXIT
NOFP
OPT
RELOC
REQUIRE
REQUIRE8 and PRESERVE8
RLIST
RN
ROUT
SETA, SETL, and SETS
SPACE or FILL
TTL and SUBT
WHILE and WEND

List of Figures

1. ASR #3
2. LSR #3
3. LSL #3
4. ROR #3
5. RRX

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AJune 2011Release for ARM Compiler toolchain v4.1 for µVision
Revision BJuly 2012Release for ARM Compiler toolchain v5.02 for µVision
Copyright © 2011-2012 ARM. All rights reserved.ARM DUI 0588B
Non-ConfidentialID062912