CoreTile Express A15x2 Technical Reference Manual: 3.3.4. Test chip SCC register descriptions

3.3.4. Test chip SCC register descriptions

This section describes the SCC registers.

Test chip SCC Register 0

The CFGREG0 Register characteristics are:

Purpose: Miscellaneous Configuration Register 0 that enables you to read and write test chip configuration settings.
Usage constraints: CFGREG0[31:30] = 00 or 11 are reserved and must not be used. These bits are valid only if CFGREG0[0] is b0.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.4 shows the bit assignments.

Figure 3.4. Test chip CFGREG0 Register bit assignments

Table 3.5 shows the bit assignments.

Table 3.5. Test chip CFGREG0 Register bit assignments

Bits	Name	Function
[31:30]	SMC remap	These map to the SMC_REMAP[1:0] bus: `b00` Reserved. `b01` CS0. `b10` CS4. `b11` Reserved. These bits are valid only if SMC is mapped to `0x0`, that is CFGREG0[0] = `b0`
[29]	CFGDISABLE	GIC configuration disable.
[28:27]	-	Reserved. Do not modify.
[26:25]	CP15_DISABLE_CPU[1:0]	Maps to the CP15_DISABLE_CPU[1:0] bus: `b0` Co-processor 15 enable. `b1` Co-processor 15 disable.
[24]	CFGBIGENDIAN_L2_Cache	Maps to the CFGBIGENDIAN_L2_Cache signal. Reserved. Do not modify.
[23:22]	-	Reserved. Do not modify.
[21:20]	CFGEND[1:0]	Maps to the CFGEND[1:0] bus. Configures CPUs as bigend.
[19]	SPNIDEN	Maps to the SPNIDEN secure non-invasive debug signal for both CPUs.
[18]	SPIDEN	Maps to the SPIDEN secure invasive debug signal for both CPUs.
[17]	NIDEN	Maps to the NIDEN non-invasive debug enable signal.
[16]	DBGEN	Maps to the DBGEN invasive debug enable signal.
[15:14]	-	Reserved. Do not modify.
[13:12]	THUMBNIT_CORE[1:0]	Thumbnit input for CPU[1:0].
[11:10]	-	Reserved. Do not modify.
[9:8]	VINITHI_CORE[1:0]	Vinithi input for CPU[1:0].
[7:4]	CLUSTER_ID	Maps to the CLUSTERID[3:0] bus.
[3]	IMININ	ICache minimum line size: `b0` 32 bytes. `b1` 64 bytes.
[2:1]	-	Reserved. Do not modify.
[0]	AXI_REMAP	NIC-301 AMBA AXI memory map: `b0` SMC mapped to `0x00_0000_0000`. `b1` AXI Master interface mapped to `0x00_0000_0000`.

Test chip SCC Register 1

The CFGREG1 Register characteristics are:

Purpose: Miscellaneous Configuration Register 1 that enables you to read and write test chip configuration settings.
Usage constraints: There are no usage constraints.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.5 shows the bit assignments.

Figure 3.5. Test chip CFGREG1 Register bit assignments

Table 3.6 shows the bit assignments.

Table 3.6. Test chip CFGREG1 Register bit assignments

Bits	Name	Function
[31:29]	-	Reserved. Do not modify.
[28]	ACP_BARE_METAL	Selects DMA bare metal access to ACP interface: `b0` DMA accesses ACP through NIC-301 fabric. `b1` DMA directly accesses ACP interface.
[27]	ACP_64N128	Selects 64-bit or 128-bit operation for the ACP interface: `b0` 128-bit ACP. `b1` 64-bit ACP.
[26]	ADDRTRANS_ACP	Translates ACP addresses `0x00_3000_0000` to `0x00_3FFF_FFFF` by overriding bit 28 of the AxADDR of the cluster ACP: `b0` `00x_E000_0000`. `b1` `00x_F000_0000`.
[25:20]	AWUSER_ACP[5:0]	ACP AWCACHE override: AWUSER[5:2] = AWCACHE[3:0] if AUSER_OVERRIDE_ACP = `b0` AWUSER[5:2] = CFGREG1[25:22] if AUSER_OVERRIDE_ACP = `b1` AWUSER[1:0] = CFGREG1[21:20]
[19:14]	ARUSER_ACP[5:0]	ACP ARCACHE override: ARUSER[5:2] = ARCACHE[3:0] if AUSER_OVERRIDE_ACP = `b0` ARUSER[5:2] = CFGREG1[19:16] if AUSER_OVERRIDE_ACP = `b1` ARUSER[1:0] = CFGREG1[15:14]
[13]	AUSER_OVERRIDE_ACP	ACP AxUSER[5:2] override enable.
[12]	AINACTS_ACP	ACP disable: `b0` ACP enabled. `b1` ACP disabled.
[11]	PHY_IDDQ	Forces DDR PHY into IDDQ power-down mode: `b0` DDR PHY enabled. `b1` DDR PHY in IDDQ power-down mode.
[10]	PHY_RESET_N	PHY reset. Release after programming the PHY through APB and LOCK signal/register is asserted.
[9]	NPRESETDBG	Resets the initialized shared debug, APB, CTI, and CTM logic in the PCLK domain. This reset operates independently of nRESET: `b0` Reset. `b1` Non-reset. The default is `b1`. See the Cortex-A15 Technical Reference Manual for information on using this internal reset.
[8]	NL2RESET	Resets the L2 logic, interrupt controller, and timer logic. This reset operates independently of nRESET: `b0` Reset. `b1` Non-reset. The default is `b1`. See the Cortex-A15 Technical Reference Manual for information on using this internal reset.
[7:6]	NDBGRESET[1:0]	Resets the debug, PTM, break-point, and watch-point in the FCLK domain. This reset operates independently of nRESET: `b0` Reset. `b1` Non-reset. The default is `b11`. See the Cortex-A15 Technical Reference Manual for information on using this internal reset.
[5:4]	NCXRESET[1:0]	Resets NEON-VFP. This reset operates independently of nRESET: `b0` Reset. `b1` Non-reset. The default is `b11`. See the Cortex-A15 Technical Reference Manual for information on using this internal reset.
[3:2]	NCORERESET[1:0]	Resets the entire CPU including NEON-VPF, debug, and PTM, but excludes break-point and watch-point logic. This reset operates independently of nRESET: `b0` Reset. `b1` Non-reset. The default is `b11`. See the Cortex-A15 Technical Reference Manual for information on using this internal reset.
[1:0]	NCPURESET[1:0]	Resets the entire CPU including NEON-VPF, debug, PTM, break-point, and watch-point logic in the FCLK domain. This reset operates independently of nRESET: `b0` Reset. `b1` Non-reset. The default is `b11`. See the Cortex-A15 Technical Reference Manual for information on using this internal reset.

Test chip SCC Register 2

The CFGREG2 Register characteristics are:

Purpose: SMC CS0 and CS1 Register that enables you to read and write match and mask bits for the SMC CS0 and SMC CS1. See Mask operation to define SMC chip select address ranges.
Usage constraints: There are no usage constraints.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.6 shows the bit assignments.

Figure 3.6. Test chip CFGREG2 Register bit assignments

Table 3.7 shows the bit assignments.

Table 3.7. Test chip CFGREG2 Register bit assignments

Bits	Name	Function
[31:24]	SMC_ADDR_MATCH0_1	SMC CS1 address match of top 8 bits
[23:16]	SMC_ADDR_MASK0_1	SMC CS1 address mask of top 8 bits
[15:8]	SMC_ADDR_MATCH0_0	SMC CS0 address match of top 8 bits
[7:0]	SMC_ADDR_MASK0_0	SMC CS0 address mask of top 8 bits

Test chip SCC Register 3

The CFGREG3 Register characteristics are:

Purpose: SMC CS2 and CS3 Register that enables you to read and write match and mask bits for the SMC CS2 and SMC CS3. See Mask operation to define SMC chip select address ranges.
Usage constraints: There are no usage constraints.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.7 shows the bit assignments.

Figure 3.7. Test chip CFGREG3 Register bit assignments

Table 3.8 shows the bit assignments.

Table 3.8. Test chip CFGREG3 Register bit assignments

Bits	Name	Function
[31:24]	SMC_ADDR_MATCH0_3	SMC CS3 address match of top 8 bits
[23:16]	SMC_ADDR_MASK0_3	SMC CS3 address mask of top 8 bits
[15:8]	SMC_ADDR_MATCH0_2	SMC CS2 address match of top 8 bits
[7:0]	SMC_ADDR_MASK0_2	SMC CS2 address mask of top 8 bits

Test chip SCC Register 4

The CFGREG4 Register characteristics are:

Purpose: SMC CS4 and CS5 Register that enables you to read and write match and mask bits for the SMC CS4. See Mask operation to define SMC chip select address ranges. SMC CS5 is reserved, and the match and mask bits for CS5 are also reserved.
Usage constraints: There are no usage constraints.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.8 shows the bit assignments.

Figure 3.8. Test chip CFGREG4 Register bit assignments

Table 3.9 shows the bit assignments.

Table 3.9. Test chip CFGREG4 Register bit assignments

Bits	Name	Function
[31:24]	-	Reserved. Do not modify.
[23:16]	-	Reserved. Do not modify.
[15:8]	SMC_ADDR_MATCH1_0	SMC CS4 address match of top 8 bits.
[7:0]	SMC_ADDR_MASK1_0	SMC CS4 address mask of top 8 bits.

Test chip SCC Register 5

The CFGREG5 Register characteristics are:

Purpose: SMC CS6 and CS7 Register that controls the match and mask bits of CS6 and CS7. See Mask operation to define SMC chip select address ranges. CS6 and CS7 are reserved, and the bits in this register are reserved.
Usage constraints: There are no usage constraints.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.9 shows the bit assignments.

Figure 3.9. Test chip CFGREG5 Register bit assignments

Table 3.10 shows the bit assignments.

Table 3.10. Test chip CFGREG5 Register bit assignments

Bits	Name	Function
[31:24]	-	Reserved. Do not modify.
[23:16]	-	Reserved. Do not modify.
[15:8]	-	Not used. Reserved. Do not modify.
[7:0]	-	Not used. Reserved. Do not modify.

Test chip SCC CUSTOMER_ID Register

The CUSTOMER_ID Register characteristics are:

Purpose: Enables you to read information about the Cortex-A15 test chip.
Usage constraints: This register is read only.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.10 shows the bit assignments.

Figure 3.10. Test chip CUSTOMER_ID Register bit assignments

Table 3.11 shows the bit assignments.

Table 3.11. Test chip CUSTOMER_ID Register bit assignments

Bits	Name	Function
[31:28]	CONFIGURATION	Cortex-A15 test chip configuration
[27:24]	MAJOR_REVISION_RN	Cortex-A15 test chip major revision number
[23:20]	MINOR_REVISION_RN	Cortex-A15 test chip minor revision number
[19:12]	DESIGNER_ID	Cortex-A15 test designer
[11:0]	PART_NUMBER	Cortex-A15 part number

Note

Figure 3.10 and Table 3.11 show a test chip that has revision number r0p0 and designer ID 41, representing ARM, and part number 0x002, representing LPAE.

Test chip SCC Register 6

The CFGREG6 Register characteristics are:

Purpose: Enables you to read the DAP ROM default target ID.
Usage constraints: This register is read only.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.11 shows the bit assignments.

Figure 3.11. Test chip CFGREG6 Register bit assignments

Table 3.12 shows the bit assignments.

Table 3.12. Test chip CFGREG6 Register bit assignments

Bits	Name	Function
[31:0]	-	DAP ROM default target ID

Test chip SCC Register 7

The CFGREG7 Register characteristics are:

Purpose: Enables you to read the DAP ROM default instance ID.
Usage constraints: This register is read only.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.12 shows the bit assignments.

Figure 3.12. Test chip CFGREG7 Register bit assignments

Table 3.13 shows the bit assignments.

Table 3.13. Test chip CFGREG7 Register bit assignments

Bits	Name	Function
[31:0]	-	DAP ROM default instance ID

Test chip SCC Register 9

The CFGREG9 Register characteristics are:

Purpose: Clock Control Register that enables you to read and write test chip clock control configuration settings.
Usage constraints: Some bit combinations are invalid. See Table 3.14.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.13 shows the bit assignments.

Figure 3.13. Test chip CFGREG9 Register bit assignments

Table 3.14 shows the bit assignments.

Table 3.14. Test chip CFGREG9 Register bit assignments

Bits	Name	Function
[31:14]	-	Reserved. Do not modify.
[13:11]	TRACECLKINRATIO	TRACECLKIN divider ratio. This divides the output of SYS PLL to derive TRACECLKIN: `b000` Divider ratio 1. `b001` Divider ratio 2. `b010` Divider ratio 3. `b011` Divider ratio 4. The default is `b011`. All other bit combinations are invalid. See Figure 2.11. Note The maximum operating frequency of TRACECLKIN is 140MHz.
[10:8]	PCLKRATIO	PCLK divider ratio. This divides the output of SYS PLL to derive PCLK. `b000` Divider ratio 1. `b001` Divider ratio 2. `b010` Divider ratio 3. `b011` Divider ratio 4. The default is `b001` All other bit combinations are invalid. See Figure 2.11. Note The maximum operating frequency of PCLK is 1500MHz.
[7:5]	ACLKRATIO	ACLK divider ratio: This divides the output of SYS PLL to derive ACLK. `b000` Divider ratio 1. `b001` Divider ratio 2. `b010` Divider ratio 3. `b011` Divider ratio 4. The default is `b001`. All other bit combinations are invalid. See Figure 2.11. Note The maximum operating frequency of ACLK is 770MHz.
[4]	AXI_SYNC_MODE	Select SYSCLK or CPU_CLK as the source for FCLK: `b0` Select CPU_CLK as the source for FCLK. The NIC-301 matrix operates asynchronously to CPU cores. `b1` Select SYSCLK as the source for FCLK. The NIC-301 matrix operates synchronously to CPU cores. The default is `b0`. See Figure 2.10. Note The maximum frequency of FCLK is 1400MHz.
[3]	DDR_SYNC_MODE	Select ACLK or DDRCLK to clock the PL341 memory interface and the DDR2 physical interface, PHY: `b0` Select DDRCLK. The PL341 memory interface and the DDR2 physical interface (PHY) operate asynchronously to AXI domain. `b1` Select ACLK. The PL341 memory interface and the DDR2 physical interface (PHY) operate synchronously with AXI domain. The default is `b0`. See Figure 2.14. Note The maximum frequency of the PL341 memory interface and DDR2 PHY clock is 400MHz.
[2]	SYS_REFCLK_SELECT	Select reference clock to SYS PLL: `b0` Select SYSREFCLK as the input reference for SYS PLL. `b1` Select CPUREFCLK as the input reference for SYS PLL. The default is `b0`. See Table 2.8. Note ARM does not recommend using the non-default option and Figure 2.10 and Figure 2.11 do not show this connection.
[1]	HDLCD_REFCLK_SELECT	Select reference clock to HDLCD PLL: `b0` Select PXLREFCLK as the input reference for SYS PLL. `b1` Select CPUREFCLK as the input reference for SYS PLL. The default is `b0`. See Table 2.8. Note The maximum frequency of PXLCLK and MMB_IDCLK is 261MHz. ARM does not recommend using the non-default option and Figure 2.10 and Figure 2.11 do not show this connection.
[0]	DDR_REFCLK_SELECT	Select reference clock to DDR PLL: `b0` Select DDRREFCLK as the input reference for SYS PLL. `b1` Select CPUREFCLK as the input reference for SYS PLL. The default is `b0`. See Table 2.8. Note The maximum value of DDRCLK is 400MHz. ARM does not recommend using the non-default option and Figure 2.10 and Figure 2.11 do not show this connection.

Test chip SCC Registers 10, 12, 14 and 16

The CFGREG10, CFGREG12, CFGREG14, and CFGREG16 Register characteristics are:

Purpose

The CFGREG10, CFGREG12, CFGREG14, and CFGREG16 registers, together with CFGREG11, CFGREG13, CFGREG15, and CFGREG17, control the PLLs that generate some of the internal clocks inside the test chip.

Two registers control each PLL as follows:

CFGREG10 and CFGREG11 control CPU PLL.
CFGREG12 and CFGREG13 control DDR PLL.
CFGREG14 and CFGREG15 control HDLCD PLL.
CFGREG16 and CFGREG17 control SYS PLL.

These registers enable you to read and write test chip CPU PLL, SYS PLL, DDR PLL, and HDLCD PLL configuration settings.

See Clocks.

Usage constraints

Bit 5 is read only.

Configurations

Not applicable.

Attributes

See Table 3.4.

Figure 3.14 shows the bit assignments.

Figure 3.14. Test chip CFGREG10, CFGREG12, CFGREG14, and CFGREG16 Register bit assignments

Table 3.15 shows the bit assignments.

Table 3.15. CFGREG10, CFGREG12, CFGREG14, and CFGREG16 Register bit assignments

Bits	Name	Function
[31:29]	-	Reserved. Do not modify.
[28:16]	x_CLKF	PLL feedback clock divider settings. Divisor = x_CLKF+1. These bits have the following default values: CFGREG10 - CPU PLL `b0001000101111`, decimal 559. CFGREG12 - DDR PLL `b0000010111111`, decimal 191. CFGREG14 - HDLCD PLL `b0000111001101`, decimal 461. CFGREG16 - SYS PLL `b0001000101111`, decimal 559. See Figure 2.11. Note See Table 2.7 for the maximum clock operating frequencies.
[15:1]	-	Reserved. Do not modify.
[0]	x_HARD_BYPASS	This bit forces the reference input clock to bypass the PLL to enable it to be driven directly into the design: `b0` Do not bypass PLL. `b1` Bypass PLL. This bit has the following default values: CFGREG10 - CPU PLL `b0`. CFGREG12 - DDR PLL `b0`. CFGREG14 - HDLCD PLL `b0`. CFGREG16 - SYS PLL `b0`. Note The `board.txt` file sets the HDLCD PLL to bypass by setting CFGREG14[0] to `b1` during the configuration process. You can set CFGREG14[0] to `b0` if you want to use the HDLCD PLL. ARM does not recommend using the other non-default options and Figure 2.10 and Figure 2.11 do not show these connections.

Test chip SCC Registers 11, 13, 15 and 17

The CFGREG11, CFGREG13, CFGREG15, and CFGREG17 Register characteristics are:

Purpose

The CFGREG11, CFGREG13, CFGREG15, and CFGREG17 registers, together with CFGREG10, CFGREG12, CFGREG14, and CFGREG16, control the PLLs that generate some of the internal clocks inside the test chip.

Two registers control each PLL as follows:

CFGREG10 and CFGREG11 control CPU PLL.
CFGREG12 and CFGREG13 control DDR PLL.
CFGREG14 and CFGREG15 control HDLCD PLL.
CFGREG16 and CFGREG17 control SYS PLL.

These registers enable you to read and write test chip CPU PLL, SYS PLL, DDR PLL, and HDLCD PLL configuration settings.

See Clocks.

Usage constraints

There are no usage constraints.

Configurations

Not applicable.

Attributes

See Table 3.4.

Figure 3.15 shows the bit assignments.

Figure 3.15. Test chip CFGREG11, CFGREG13, CFGREG15, and CFGREG17 Register bit assignments

Table 3.16 shows the bit assignments.

Table 3.16. Test chip CFGREG11, CFGREG13, CFGREG15, and CFGREG17 Register bit assignments

Bits	Name	Function
[31:12]	-	Reserved. Do not modify.
[11:8]	x_CLKOD	PLL output divider settings. Divisor = x_CLOD+1. These bits have the following default values: CFGREG11- CPU PLL `b0001`. CFGREG13 - DDR PLL `b0101`. CFGREG15 - HDLCD PLL `b1101`. CFGREG17 - SYS PLL `b1101`. See Figure 2.11. Note See Table 2.7 for the maximum clock operating frequencies.
[7:6]	-	Reserved. Do not modify.
[5:0]	x_CLKR	PLL reference clock divider settings. Divisor = x_CLKR+1. These bits have the following default values: CFGREG11 - CPU PLL `b001101`. CFGREG13 - DDR PLL `b000011`. CFGREG15 - HDLCD PLL `b001001`. CFGREG17 - SYS PLL `b001101`. See Figure 2.11. Note See Table 2.7 for the maximum clock operating frequencies.

Test chip SCC Register 22

The CFGREG22 Register characteristics are:

Purpose: DMAC register 0 that enables you to read from and write control signals to the Dynamic Memory Access Controller (DMAC), DMA-330.
Usage constraints: There are no usage constraints.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.16 shows the bit assignments.

Figure 3.16. Test chip CFGREG22 Register bit assignments

Table 3.17 shows the bit assignments.

Table 3.17. Test chip CFGREG22 Register bit assignments

Bits	Name	Function
[31:20]	-	Reserved. Do not modify.
[19:16]	DMA_IRQS_NS[3:0]	These bits control the security state of the interrupt outputs when the DMAC exits from reset: DMA_IRQ_NS[x] = `b0` The DMAC assigns IRQ[x] to the Secure state. DMA_IRQ_NS[x] = `b1` The DMAC assigns IRQ[x] to the Non-secure state. See the AMBA DMA Controller DMA-330 Technical Reference Manual.
[15:10]	-	Reserved. Do not modify.
[9:8]	DMA_PERIPH_NS[1:0]	Boot peripherals security state. These bits control the security state of the peripheral request interface when the DMAC exits from reset: DMA_PERIPH_NS[x] = `b0` The DMAC assigns peripheral request interface[x] to the Secure state. DMA_PERIPH_NS[x] = `b1` The DMAC assigns peripheral interface request interface[x] to the Non-secure state.
[7:5]	-	Reserved. Do not modify.
[4]	DMA_BOOT_NS	Boot manager security state. When the DMAC exits from reset, this bit controls the security state of the DMA manager thread: `b0` Assigns DMA manager to the Secure state. `b1` Assigns DMA manager to the Non-secure state.
[3:1]	-	Reserved. Do not modify.
[0]	DMA_BOOT_FRM_PC	Boot from program counter. This controls the location of where the DMAC executes its initial instruction after it exits from reset: `b0` The DMAC waits for an instruction from the APB interface. `b1` The DMAC executes the instruction that is located at the address that DMAC register 1 provides. See Test chip SCC Register 23.

Test chip SCC Register 23

The CFGREG23 Register characteristics are:

Purpose: DMAC register 1 that enables you to read from and write control signals to the Dynamic Memory Access Controller (DMAC), DMA-330.
Usage constraints: There are no usage constraints.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.17 shows the bit assignments.

Figure 3.17. Test chip CFGREG23 Register bit assignments

Table 3.18 shows the bit assignments.

Table 3.18. Test chip CFGREG23 Register bit assignments

Bits	Name	Function
[31:0]	DMA_BOOT_ADDR	Boot address for the DMAC. This configures the address location that contains the first instruction that the DMAC executes when it exits from reset. Note The DMAC uses this address only when DMA_BOOT_FRM_PC is HIGH. See Test chip SCC Register 22.

Test chip SCC Register APB_CLEAR

The APB_CLEAR Register characteristics are:

Purpose: Writing 0xA50FF0FA to the APB_CLEAR register reverts all SCC registers to their test chip default values.
Usage constraints: There are no usage constraints.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.18 shows the bit assignments.

Figure 3.18. Test chip APB_CLEAR Register bit assignments

Table 3.19 shows the bit assignments.

Table 3.19. Test chip APB_CLEAR Register bit assignments

Bits	Name	Function
[31:0]	-	Writing `0xA50FF0FA` to this register reverts the SCC registers to their test chip default values. Note ARM recommends that you do not write to this register.

Test chip SCC Register TC_ID

The DEVICEID Register characteristics are:

Purpose: Enables you to read the Cortex-A15 MPCore test chip specific device ID.
Usage constraints: This register is read-only.
Configurations: Not applicable.
Attributes: See Table 3.4.

Figure 3.19 shows the bit assignments.

Figure 3.19. Test chip TC_ID Register bit assignments

Table 3.20 shows the bit assignments.

Table 3.20. Test chip TC_ID Register bit assignments

Bits	Name	Function
[31:0]	Cortex-A15 test chip specific device ID	Cortex-A15 test chip device ID. The default is `0x00050176`.

Test chip SCC Register CPU_ID

The CPUID Register characteristics are:

Purpose: Enables you to read the Cortex-A15 MPCore test chip CPU ID.
Usage constraints: This register is read-only.
Configurations: Not applicable.
Attributes: Table 3.4.

Figure 3.20 shows the bit assignments.

Figure 3.20. Test chip CPU_ID Register bit assignments

Table 3.21 shows the bit assignments.

Table 3.21. Test chip CPUID Register bit assignments

Bits	Name	Function
[31:0]	-	Cortex-A15 CPU ID

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