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This section describes the HDLCD controller registers. Table B.1 provides cross references to individual registers.
The VERSION Register characteristics are:
Holds a static version number for the LCD controller. Changes to the processor that affect registers and data structures increment the VERSION_MAJOR value and reset the VERSION_MINOR value.
Other changes that do not affect the binary compatibility only increment the VERSION_MINOR number.
There are no usage constraints.
Available in all HDLCD configurations.
See Table B.1.
Figure B.1 shows the bit assignments.
Table B.2 shows the bit assignments.
Table B.2. Version Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:16] | PRODUCT_ID | Product ID number 0x1CDC |
| [15:8] | VERSION_MAJOR | These bits provide the major product version information. For release r0p0, the value is |
| [7:0] | VERSION_MINOR | These bits provide the minor product version information. For release r0p0, the value is |
The INT_RAWSTAT Register characteristics are:
Shows the unmasked status of the interrupt sources. Writing a 1 to the bit of an interrupt source forces this bit to be set and generate an interrupt if it is not masked by the corresponding bit in the Interrupt Mask Register. Writing a 0 to the bit of an interrupt source has no effect.
Use the Interrupt Clear Register to clear interrupts.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.2 shows the bit assignments.
Table B.3 shows the bit assignments.
Table B.3. Interrupt Raw Status Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:4] | - | Reserved, write as zero, read undefined. |
| [3] | UNDERRUN | No data was available to display while DATAEN was active. This interrupt triggers if the controller does not have pixel data available to drive when DATAEN is active. When this occurs, the controller drives the default color for the rest of the screen and attempts to display the next frame correctly. |
| [2] | VSYNC | Vertical sync is active. This interrupt triggers at the moment the VSYNC output goes active. |
| [1] | BUS_ERROR | The DMA module received a bus error while reading data. This interrupt triggers if any frame buffer read operation ever reports an error. |
| [0] | DMA_END | The DMA module has finished reading a frame. This interrupt triggers when the last piece of data for a frame has been read. The DMA immediately continues on the next frame, so this interrupt only ensures that the frame buffer for the previous frame is no longer required. |
The INT_CLEAR Register characteristics are:
Clears interrupt sources. Writing a 1 to the bit of an asserted source clears the interrupt in the Interrupt Raw Status Register, and in the Interrupt Status Register, if it is not masked.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.3 shows the bit assignments.
Table B.4 shows the bit assignments.
Table B.4. Interrupt Clear Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:4] | - | Reserved, write as zero. |
| [3] | UNDERRUN | No data was available to display while DATAEN was active. This interrupt triggers if the controller does not have pixel data available to drive when DATAEN is active. When this occurs, the controller drives the default color for the rest of the screen and attempts to display the next frame correctly. |
| [2] | VSYNC | Vertical sync is active. This interrupt triggers at the moment the VSYNC output goes active. |
| [1] | BUS_ERROR | The DMA module received a bus error while reading data. This interrupt triggers if any frame buffer read operation ever reports an error. |
| [0] | DMA_END | The DMA module has finished reading a frame. This interrupt triggers when the last piece of data for a frame has been read. The DMA immediately continues on the next frame, so this interrupt only ensures that the frame buffer for the previous frame is no longer required. |
The INT_MASK Register characteristics are:
Holds the bit mask that enables an interrupt source if the corresponding mask bit is set to 1.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.4 shows the bit assignments.
Table B.5 shows the bit assignments.
Table B.5. Interrupt Mask Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:4] | - | Reserved, write as zero, read undefined. |
| [3] | UNDERRUN | No data was available to display while DATAEN was active. This interrupt triggers if the controller does not have pixel data available to drive when DATAEN is active. When this occurs, the controller drives the default color for the rest of the screen and attempts to display the next frame correctly. |
| [2] | VSYNC | Vertical sync is active. This interrupt triggers at the moment the VSYNC output goes active. |
| [1] | BUS_ERROR | The DMA module received a bus error while reading data. This interrupt triggers if any frame buffer read operation ever reports an error. |
| [0] | DMA_END | The DMA module has finished reading a frame. This interrupt triggers when the last piece of data for a frame has been read. The DMA immediately continues on the next frame, so this interrupt only ensures that the frame buffer for the previous frame is no longer required. |
The INT_STATUS Register characteristics are:
Interrupt Raw Status Register ANDed with the Interrupt Mask Register and shows the active and masked interrupt sources. Bits selected by the Interrupt Mask Register are active in the Interrupt Status Register. These bits show the status of the interrupt sources. Bits not selected by the Interrupt Mask Register are inactive. If any of the sources are asserted in the Interrupt status Register, then the external IRQ line is asserted.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.5 shows the bit assignments.
Table B.6 shows the bit assignments.
Table B.6. Interrupt Status Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:4] | - | Reserved, read undefined. |
| [3] | UNDERRUN | No data was available to display while DATAEN was active. This interrupt triggers if the controller does not have pixel data available to drive when DATAEN is active. When this occurs, the controller drives the default color for the rest of the screen and attempts to display the next frame correctly. |
| [2] | VSYNC | Vertical sync is active. This interrupt triggers at the moment the VSYNC output goes active. |
| [1] | BUS_ERROR | The DMA module received a bus error while reading data. This interrupt triggers if any frame buffer read operation ever reports an error. |
| [0] | DMA_END | The DMA module has finished reading a frame. This interrupt triggers when the last piece of data for a frame has been read. The DMA immediately continues on the next frame, so this interrupt only ensures that the frame buffer for the previous frame is no longer required. |
The FB_BASE Register characteristics are:
Holds the address of the first pixel of the first line in the frame buffer.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.6 shows the bit assignments.
Table B.7 shows the bit assignments.
Table B.7. Frame Buffer Base Address Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:3] | FB_BASE_ADDR | Frame buffer base address |
| [2:0] | Reserved | Reserved, write as zero, read undefined |
The FB_LINE_LENGTH Register characteristics are:
Holds the length of each frame buffer line in bytes.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.7 shows the bit assignments.
Table B.8 shows the bit assignments.
Table B.8. Frame Buffer Line Length Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:3] | FB_LINE_LENGTH | Frame buffer line length |
| [2:0] | - | Reserved, write as zero, read undefined |
The FB_LINE_COUNT Register characteristics are:
Holds the number of lines to read from the frame buffer.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.8 shows the bit assignments.
Table B.9 shows the bit assignments.
Table B.9. Frame Buffer Line Count Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined |
| [11:0] | FB_LINE_COUNT | Frame buffer line count |
The FB_LINE_PITCH Register characteristics are:
Holds the number of bytes between the start of one line in the frame buffer and the start of the next line. This value is treated as a signed 2’s complement number, enabling negative pitch if required.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.9 shows the bit assignments.
Table B.10 shows the bit assignments.
Table B.10. Frame Buffer Line Count Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:3] | FB_LINE_PITCH | Frame buffer line pitch |
| [2:0] | - | Reserved, write as zero, read undefined |
The BUS_OPTIONS Register characteristics are:
Controls aspects of how the LCD controller accesses the bus. This value can be tuned to better match the characteristics of the memory controller and other units in the system.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.10 shows the bit assignments.
Table B.11 shows the bit assignments.
Table B.11. Bus Options Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined. |
| [11:8] | MAX_OUTSTANDING | Maximum number of outstanding requests the LCD controller is permitted to have on the bus at any time. CautionA value of zero disables all bus transfers. |
| [7:5] | - | Reserved, write as zero, read undefined. |
| [4] | BURST_16 | Permit the use of 16-beat bursts. |
| [3] | BURST_8 | Permit the use of 8-beat bursts. |
| [2] | BURST_4 | Permit the use of 4-beat bursts. |
| [1] | BURST_2 | Permit the use of 2-beat bursts. |
| [0] | BURST_1 | Permit the use of 1-beat bursts. |
If the scan line length does not end up at a multiple of the permitted burst lengths, the controller uses smaller bursts to read the remaining few pixels in each scan line. If no bursts are permitted, this mechanism also triggers, and has the same effect as permitting all bursts.
Incorrectly configuring this register can degrade the performance of both the LCD controller and the rest of the system.
The V_SYNC Register characteristics are:
Holds the width of the vertical synch signal, counted in number of horizontal scan lines.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.11 shows the bit assignments.
Table B.12 shows the bit assignments.
Table B.12. Vertical Synch Width Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined |
| [11:0] | V_SYNC | Vertical synch width -1 |
The V_BACK_PORCH Register characteristics are:
Holds the width of the interval between the vertical sync and the first visible line, counted in the number of horizontal scan lines.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.12 shows the bit assignments.
Table B.13 shows the bit assignments.
Table B.13. Vertical Back Porch Width Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined |
| [11:0] | V_BACK_PORCH | Vertical back porch width -1 |
The V_DATA Register characteristics are:
Holds the width of the vertical data area, that is, the number of visible lines, counted in the number of horizontal scan lines.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.13 shows the bit assignments.
Table B.14 shows the bit assignments.
Table B.14. Vertical Data Width Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined |
| [11:0] | V_DATA | Vertical data width -1 |
The V_FRONT_PORCH Register characteristics are:
Holds the width of the interval between the last visible line and the next vertical synchronization, counted in the number of horizontal scan lines.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.14 shows the bit assignments.
Table B.15 shows the bit assignments.
Table B.15. Vertical Front Porch Width Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined |
| [11:0] | V_FRONT_PORCH | Vertical front porch width -1 |
The H_SYNCH Register characteristics are:
Holds the width of the horizontal synch signal, counted in pixel clocks.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.15 shows the bit assignments.
Table B.16 shows the bit assignments.
Table B.16. Horizontal Synch Width Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined |
| [11:0] | H_SYNC | Horizontal synch width -1 |
The H_BACK_PORCH Register characteristics are:
Holds the width of the interval between the horizontal sync and the first visible column, counted in pixel clocks.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.16 shows the bit assignments.
Table B.17 shows the bit assignments.
Table B.17. Horizontal Back Porch Width Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined |
| [11:0] | H_BACK_PORCH | Horizontal back porch width -1 |
The H_DATA Register characteristics are:
Holds the width of the horizontal data area, that is, the number of visible columns counted in pixel clocks.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.17 shows the bit assignments.
Table B.18 shows the bit assignments.
Table B.18. Horizontal Data Width Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined |
| [11:0] | H_DATA | Horizontal data width -1 |
The H_FRONT_PORCH Register characteristics are:
Holds the width of the interval between the last visible column and the next horizontal synchronization, counted in pixel clocks.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.18 shows the bit assignments.
Table B.19 shows the bit assignments.
Table B.19. Horizontal Front Porch Width Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved, write as zero, read undefined |
| [11:0] | H_FRONT_PORCH | Horizontal front porch width -1 |
The POLARITIES Register characteristics are:
Controls the polarities of the synchronization signals and PXLCLK that is exported from the CoreTile Express A15×2 daughterboard.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.19 shows the bit assignments.
Table B.20 shows the bit assignments.
Table B.20. Polarities Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:5] | - | Reserved, write as zero, read undefined. |
| [4] | PXLCLK_POLARITY | Holds the value of the PXLCLKPOL output. This is intended to be used to control the polarity of the pixel clock that is exported from the CoreTile Express A15×2 daughterboard. Note
|
| [3] | DATA_POLARITY | Holds the active level of the DATA output. |
| [2] | DATAEN_POLARITY | Holds the active level of the DATAEN output. |
| [1] | HSYNC_POLARITY | Holds the active level of the HSYNC output. |
| [0] | VSYNC_POLARITY | Holds the active level of the VSYNC output. |
The COMMAND Register characteristics are:
Starts and stops the LCD controller.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.20 shows the bit assignments.
Table B.21 shows the bit assignments.
Table B.21. Command Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:1] | - | Reserved, write as zero, read undefined |
| [0] | ENABLE | Enable the LCD controller |
The PIXEL_FORMAT Register characteristics are:
BYTES_PER_PIXEL plus one bytes are extracted from the internal buffer. The extracted bytes are used to form a 32-bit value. The individual bytes are then optionally reordered if BIG_ENDIAN is set before the color components are extracted.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.21 shows the little endian byte layout.
Figure B.22 shows the big endian byte layout.
Figure B.23 shows the bit assignments for the big endian format.
Table B.22 shows the bit assignments for the big endian format.
Table B.22. Pixel Format Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31] | BIG_ENDIAN | Use big endian byte order |
| [30:5] | - | Reserved, write as zero, read undefined |
| [4:3] | BYTES_PER_PIXEL | Number of bytes to extract from the buffer for each pixel to display, minus one |
| [2:0] | - | Reserved, write as zero, read undefined |
The RED_SELECT, GREEN_SELECT, and BLUE_SELECT Registers characteristics are:
The bytes extracted from the internal buffer are presented as a 32-bit value. These registers select how many bits, and at which position, are used to extract and use as the red, green, and blue color components. If no bits are extracted, or no data is available, the default color is used.
There are no usage constraints.
Available in all HDLCD controller configurations.
See Table B.1.
Figure B.24 shows the bit assignments.
Table B.23 shows the bit assignments.
Table B.23. Color Select Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:24] | - | Reserved, write as zero, read undefined. |
| [23:16] | DEFAULT | Default color. This color is used if SIZE is zero, if the buffer underruns, or while outside the visible frame area. |
| [15:12] | - | Reserved, write as zero, read undefined. |
| [11:8] | SIZE | Number of bits to extract: If this value is zero, the default color is used. If this value is in the range 1-7, the extracted MSBs are repeated for the LSBs until eight bits are reached. If this value is larger than eight, the behavior is UNDEFINED. |
| [7:5] | - | Reserved, write as zero, read undefined. |
| [4:0] | OFFSET | Index of the lowest bit to extract. If OFFSET + SIZE >= 8 + 8 x BYTES_PER_PIXEL, the behavior is UNDEFINED. |
| Copyright © 2011-2013 ARM. All rights reserved. | ARM DUI 0604E |
| Non-Confidential | ID040613 |
| PDF version | |
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