4.9. Access control

Control of the optional L1 cache ECC and attribute override, the priority of AHB slave traffic, and whether an access is mapped to TCM interfaces or AXI master interface, is defined by the access control registers. The access control registers are:

Table 4.68.  Access control register summary

AddressName Type

Required

privilege

Reset

value

Description
0xE000EF90ITCMCRRWPrivileged0x00000000[a]Instruction and Data Tightly-Coupled Memory Control Registers
0xE000EF94DTCMCRRWPrivileged0x00000000[a]
0xE000EF98AHBPCRRWPrivileged0x00000000[a]AHBP Control Register
0xE000EF9CCACRRWPrivileged-[b]L1 Cache Control Register
0xE000EFA0AHBSCRRWPrivileged0x00000800AHB Slave Control Register
0xE000EFA8ABFSRRWPrivileged0x00000000Auxiliary Bus Fault Status register

[a] Implementation defined.

[b] The reset value is implementation and configuration dependent and the silicon vendor changes this. If cache ECC is configured the reset value is 0x00000000, if cache ECC is not configured the reset value is 0x00000002.


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