3.4.6. LDM and STM

Load and Store Multiple registers.

Syntax

op{addr_mode}{cond} Rn{!}, reglist

Where:

op

Is one of:

LDM

Load Multiple registers.

STM

Store Multiple registers.

addr_mode

Is any one of the following:

IA

Increment address After each access. This is the default.

DB

Decrement address Before each access.

cond

Is an optional condition code. See Conditional execution.

Rn

Is the register on which the memory addresses are based.

!

Is an optional writeback suffix. If ! is present the final address, that is loaded from or stored to, is written back into Rn.

reglist

Is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range, see Examples.

LDMIA and LDMFD are synonyms for LDM. LDMFD refers to its use for popping data from Full Descending stacks.

LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks.

STMIA and STMEA are synonyms for STM. STMEA refers to its use for pushing data onto Empty Ascending stacks.

STMFD is a synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks.

Operation

LDM instructions load the registers in reglist with word values from memory addresses based on Rn.

STM instructions store the word values in the registers in reglist to memory addresses based on Rn.

For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn.

For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn.

The PUSH and POP instructions can be expressed in this form. See PUSH and POP for details.

Restrictions

In these instructions:

  • Rn must not be PC.

  • reglist must not contain SP.

  • In any STM instruction, reglist must not contain PC.

  • In any LDM instruction, reglist must not contain PC if it contains LR.

  • reglist must not contain Rn if you specify the writeback suffix.

When PC is in reglist in an LDM instruction:

  • Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned address.

  • If the instruction is conditional, it must be the last instruction in the IT block.

Condition flags

These instructions do not change the flags.

Examples

    LDM     R8,{R0,R2,R9}      ; LDMIA is a synonym for LDM.
    STMDB   R1!,{R3‑R6,R11,R12}

Incorrect examples

    STM     R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable. 
    LDM     R2, {}         ; There must be at least one register in the list.
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