4.5.4. Cache Size Selection Register

The CSSELR selects the cache whose configuration is currently visible in the CCSIDR. See the register summary in Table 4.39 for its attributes The bit assignments are:

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Table 4.44. CSSELR bit assignments

BitNameDescription
[31:4]-Reserved.
[3:1]Level

Identifies the cache level selected:

0b000

Level 1 cache.

This field is read only, writes are ignored.

[0]InD

Enables selection of instruction or data cache:

0

Data cache.

1

Instruction cache.


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