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Home > The Cortex-M7 Instruction Set > Multiply and divide instructions > MUL, MLA, and MLS |

Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32‑bit operands, and producing a 32-bit result.

`MUL{S}`

{} {`cond`

,}`Rd`

,`Rn`

; Multiply`Rm`

`MLA`

{}`cond`

,`Rd`

,`Rn`

,`Rm`

; Multiply with accumulate`Ra`

`MLS`

{}`cond`

,`Rd`

,`Rn`

,`Rm`

; Multiply with subtract`Ra`

Where:

`cond`

Is an optional condition code. See

*Conditional execution*.`S`

Is an optional suffix. If

is specified, the condition code flags are updated on the result of the operation, see`S`

*Conditional execution*.`Rd`

Is the destination register. If

is omitted, the destination register is`Rd`

.`Rn`

`Rn, Rm`

Are registers holding the values to be multiplied.

`Ra`

Is a register holding the value to be added or subtracted from.

The `MUL`

instruction multiplies the values from

and `Rn`

,
and places the least significant 32 bits of the result in

`Rd`

The `MLA`

instruction multiplies the values from

and `Rn`

,
adds the value from

`Ra`

`Rd`

The `MLS`

instruction multiplies the values from

and `Rn`

,
subtracts the product from the value from

`Ra`

`Rd`

The results of these instructions do not depend on whether the operands are signed or unsigned.

In these instructions, do not use SP and do not use PC.

If you use the * S* suffix with the

`MUL`

instruction:,`Rd`

, and`Rn`

must all be in the range`Rm`

`R0`

-`R7`

.must be the same as`Rd`

.`Rm`

You must not use the

suffix.`cond`

The MLA instruction and MULS instructions:

Update the N and Z flags according to the result.

Do not affect the C and V flags.