4.5.5. Instruction Error bank Register 0-1

The IEBR0-1 characteristics are:

Purpose

Stores information about the error detected in the instruction cache during a cache lookup.

Usage Constraints

Accessible in privileged mode only.

Configurations

Available if the ECC configurable option is implemented.

Attributes

See the register summary in Table 3.1.

Figure 4.1 shows the IEBR0-1 bit assignments.

Figure 4.1.  IEBR0-1 bit assignments

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Table 4.45 shows the IEBR0-1 bit assignments.

Table 4.45. IEBR0-1 bit assignments

BitsNameTypeDescription
[31:30]-RWUser-defined. Error detection logic sets this field to 0b00 on a new allocation and on powerup reset.
[29:18]-RWReserved.
[17]Type of errorRW

Indicates the error type:

0

Correctable error.

1

Non-correctable error[a].

[16]RAM bankRW

Indicates which RAM bank to use:

0

Tag RAM.

1

Data RAM.

[15:2]RAM locationRW

Indicates the location in instruction cache RAM:

[14]

Way.

[13:4]

Index.

[3:2]

Line doubleword offset.

[1]

Locked

RW

Indicates whether the location is locked or not locked:

0

Location is not locked and available for hardware to allocate.

1

Location is locked by software. Hardware is not allowed to allocate to this entry.

Reset by powerup reset to 0.

[0]ValidRW

Indicates whether the entry is valid or not:

0

Entry is invalid.

1

Entry is valid.

Reset by powerup reset to 0.

[a] Non-correctable errors are recorded when errors are found in multiple bits of the data read from the RAM. These errors result in data loss or data corruption and therefore are non-recoverable.


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