4.5.1. Cache Level ID Register

The CLIDR identifies the type of cache, or caches, implemented at each level, and the level of coherency and unification. See the register summary in Table 4.39 for its attributes. The bit assignments are:

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Table 4.40. CLIDR bit assignments

Bits NameFunction
[31:30]-SBZ.
[29:27]LoU

Level of Unification:

0b001

Level 2, if either cache is implemented.

0b000

Level 1, if neither instruction nor data cache is implemented.

[26:24]LoC

Level of Coherency:

0b001

Level 2, if either cache is implemented.

0b000

Level 1, if neither instruction nor data cache is implemented.

[23:21]LoUISRAZ.
[20:18]CL 7
0b000

No cache at CL 7.

[17:15]CL 6
0b000

No cache at CL 6.

[14:12]CL 5
0b000

No cache at CL 5.

[11:9]CL 4
0b000

No cache at CL 4.

[8:6]CL 3
0b000

No cache at CL 3.

[5:3]CL 2
0b000

No cache at CL 2.

[2]CL 1
RAZ

Indicates no unified cache at CL1.

[1]CL 1
1

Data cache is implemented.

0

No data cache is implemented.

[0]CL 1
1

An instruction cache is implemented.

0

No instruction cache is implemented.


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