4.5.3. Cache Size ID Register

The CCSIDR identifies the configuration of the cache currently selected by the CSSELR. If no instruction or data cache is configured, the corresponding CCSIDR is RAZ. See the register summary in Table 4.39 for its attributes. The bit assignments are:

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Table 4.42. CCSIDR bit assignments

Bits

Name Function[a]
[31]WT

Indicates support available for Write-Through:

1

Write-Through support available.

[30]WB

Indicates support available for Write-Back:

1

Write-Back support available.

[29]RA

Indicates support available for read allocation:

1

Read allocation support available.

[28]WA

Indicates support available for write allocation:

1

Write allocation support available.

[27:13]NumSets

Indicates the number of sets as:

(number of sets) - 1.

[12:3]Associativity

Indicates the number of ways as:

(number of ways) - 1.

[2:0]LineSizeIndicates the number of words in each cache line.

[a] See Table 4.43 for valid bit field encodings.


The LineSize field is encoded as 2 less than log(2) of the number of words in the cache line. For example, a value of 0x0 indicates there are four words in a cache line, that is the minimum size for the cache. A value of 0x1 indicates there are eight words in a cache line.

Table 4.43 shows the individual bit field and complete register encodings for the CCSIDR. Use this to determine the cache size for the L1 data or instruction cache selected by the Cache Size Selection Register (CSSELR). See Cache Size Selection Register.

Table 4.43. CCSIDR encodings

CSSELRCacheSizeComplete register encodingRegister bit field encoding
WTWBRAWANumSetsAssociativity LineSize
0x0Data cache4KB0xF003E01911110x001F0x30x1
8KB0xF007E0190x003F
16KB0xF00FE0190x007F
32KB0xF01FE0190x00FF
64KB0xF03FE0190x01FF
0x1Instruction cache4KB0xF007E00911110x003F0x10x1
8KB0xF00FE0090x007F
16KB0xF01FE0090x00FF
32KB0xF03FE0090x01FF
64KB0xF07FE0090x03FF

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