3.5.1. ADD, ADC, SUB, SBC, and RSB

Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.

Syntax

op{S}{cond} {Rd,} Rn, Operand2             ; ADD; ADC; SBC; RSB
op{S|W}{cond} {Rd,} Rn, #imm12             ; ADD; SUB

Where:

op

Is one of:

ADD

Add.

ADC

Add with Carry.

SUB

Subtract.

SBC

Subtract with Carry.

RSB

Reverse Subtract.

S

Is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see Conditional execution.

cond

Is an optional condition code. See Conditional execution.

Rd

Is the destination register. If Rd is omitted, the destination register is Rn.

Rn

Is the register holding the first operand.

Operand2

Is a flexible second operand. See Flexible second operand for details of the options.

imm12

Is any value in the range 0-4095.

Operation

The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.

The ADC instruction adds the values in Rn and Operand2, together with the carry flag.

The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.

The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one.

The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2.

Use ADC and SBC to synthesize multiword arithmetic, see Multiword arithmetic examples.

See also ADR.

Note

ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses the imm12 operand.

Restrictions

In these instructions:

  • Operand2 must not be SP and must not be PC.

  • Rd can be SP only in ADD and SUB, and only with the additional restrictions:

    • Rn must also be SP.

    • Any shift in Operand2 must be limited to a maximum of 3 bits using LSL.

  • Rn can be SP only in ADD and SUB.

  • Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:

    • You must not specify the S suffix.

    • Rm must not be PC and must not be SP.

    • If the instruction is conditional, it must be the last instruction in the IT block.

  • with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions:

    • You must not specify the S suffix.

    • The second operand must be a constant in the range 0-4095.

    Note

    • When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00 before performing the calculation, making the base address for the calculation word-aligned.

    • If you want to generate the address of an instruction, you have to adjust the constant based on the value of the PC. Arm recommends that you use the ADR instruction instead of ADD or SUB with Rn equal to the PC, because your assembler automatically calculates the correct constant for the ADR instruction.

When Rd is PC in the ADD{cond} PC, PC, Rm instruction:

  • Bit[0] of the value written to the PC is ignored.

  • A branch occurs to the address created by forcing bit[0] of that value to 0.

Condition flags

If S is specified, these instructions update the N, Z, C and V flags according to the result.

Examples

    ADD     R2, R1, R3
    SUBS    R8, R6, #240        ; Sets the flags on the result.
    RSB     R4, R4, #1280       ; Subtracts contents of R4 from 1280.
    ADCHI   R11, R0, R3         ; Only executed if C flag set and Z.
                                ; flag clear.

Multiword arithmetic examples

Example 3.4 shows two instructions that add a 64‑bit integer contained in R2 and R3 to another 64‑bit integer contained in R0 and R1, and place the result in R4 and R5.

Example 3.4. 64-bit addition

    ADDS    R4, R0, R2    ; Add the least significant words.
    ADC     R5, R1, R3    ; Add the most significant words with carry.

Multiword values do not have to use consecutive registers. Example 3.5 shows instructions that subtract a 96‑bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2.

Example 3.5. 96-bit subtraction

    SUBS    R6, R6, R9     ; Subtract the least significant words.
    SBCS    R9, R2, R1     ; Subtract the middle words with carry.
    SBC     R2, R8, R11    ; Subtract the most significant words with carry.

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