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Home > The Cortex-M7 Instruction Set > General data processing instructions > ADD, ADC, SUB, SBC, and RSB |

Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.

{S}{`op`

} {`cond`

,}`Rd`

,`Rn`

; ADD; ADC; SBC; RSB`Operand2`

{S|W}{`op`

} {`cond`

,}`Rd`

, #`Rn`

; ADD; SUB`imm12`

Where:

`op`

Is one of:

`ADD`

Add.

`ADC`

Add with Carry.

`SUB`

Subtract.

`SBC`

Subtract with Carry.

`RSB`

Reverse Subtract.

`S`

Is an optional suffix. If

is specified, the condition code flags are updated on the result of the operation, see`S`

*Conditional execution*.`cond`

Is an optional condition code. See

*Conditional execution*.`Rd`

Is the destination register. If

is omitted, the destination register is`Rd`

.`Rn`

`Rn`

Is the register holding the first operand.

`Operand2`

Is a flexible second operand. See

*Flexible second operand*for details of the options.`imm12`

Is any value in the range 0-4095.

The `ADD`

instruction adds the value of or

`imm12`

`Rn`

.The `ADC`

instruction adds the values in

and `Rn`

,
together with the carry flag.

The `SUB`

instruction subtracts the value of or

`imm12`

`Rn`

The `SBC`

instruction subtracts the value of from
the value in

`Rn`

The `RSB`

instruction subtracts the value in from
the value of

`Operand2`

`Operand2`

Use `ADC`

and `SBC`

to synthesize multiword
arithmetic, see *Multiword arithmetic examples*.

See also *ADR*.

`ADDW`

is equivalent to the `ADD`

syntax
that uses the

operand. `imm12`

`SUBW`

is
equivalent to the `SUB`

syntax that uses the

operand.`imm12`

In these instructions:

must not be SP and must not be PC.`Operand2`

can be SP only in`Rd`

`ADD`

and`SUB`

, and only with the additional restrictions:must also be SP.`Rn`

Any shift in

must be limited to a maximum of 3 bits using`Operand2`

`LSL`

.

can be SP only in`Rn`

`ADD`

and`SUB`

.can be PC only in the`Rd`

`ADD{`

instruction where:} PC, PC, Rm`cond`

You must not specify the S suffix.

must not be PC and must not be SP.`Rm`

If the instruction is conditional, it must be the last instruction in the IT block.

with the exception of the

`ADD{`

instruction,} PC, PC, Rm`cond`

can be PC only in`Rn`

`ADD`

and`SUB`

, and only with the additional restrictions:You must not specify the S suffix.

The second operand must be a constant in the range 0-4095.

### Note

When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to

`0b00`

before performing the calculation, making the base address for the calculation word-aligned.If you want to generate the address of an instruction, you have to adjust the constant based on the value of the PC. Arm recommends that you use the

`ADR`

instruction instead of`ADD`

or`SUB`

withequal to the PC, because your assembler automatically calculates the correct constant for the`Rn`

`ADR`

instruction.

When

is PC
in the `Rd`

`ADD{`

instruction:* cond*} PC, PC,

`Rm`

Bit[0] of the value written to the PC is ignored.

A branch occurs to the address created by forcing bit[0] of that value to 0.

If * S* is specified, these instructions
update the N, Z, C and V flags according to the result.

ADD R2, R1, R3 SUBS R8, R6, #240 ; Sets the flags on the result. RSB R4, R4, #1280 ; Subtracts contents of R4 from 1280. ADCHI R11, R0, R3 ; Only executed if C flag set and Z. ; flag clear.

Example 3.4 shows
two instructions that add a 64‑bit integer contained in * R2* and

`R3`

`R0`

`R1`

`R4`

`R5`

**Example 3.4. 64-bit addition**

ADDS R4, R0, R2 ; Add the least significant words. ADC R5, R1, R3 ; Add the most significant words with carry.

Multiword values do not have to use consecutive registers. Example 3.5 shows instructions that subtract a 96‑bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2.

**Example 3.5. 96-bit subtraction**

SUBS R6, R6, R9 ; Subtract the least significant words. SBCS R9, R2, R1 ; Subtract the middle words with carry. SBC R2, R8, R11 ; Subtract the most significant words with carry.