3.4.3. LDR and STR, register offset

Load and Store with register offset.


op{type}{cond} Rt, [Rn, Rm {, LSL #n}]



Is one of:


Load Register.


Store Register.


Is one of:


Unsigned byte, zero extend to 32 bits on loads.


Signed byte, sign extend to 32 bits (LDR only).


Unsigned halfword, zero extend to 32 bits on loads.


Signed halfword, sign extend to 32 bits (LDR only).

omit, for word.


Is an optional condition code. See Conditional execution.


Is the register to load or store.


Is the register on which the memory address is based.


Is a register containing a value to be used as the offset.

LSL #n

Is an optional shift, with n in the range 0-3.


LDR instructions load a register with a value from memory.

STR instructions store a register value into memory.

The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL.

The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See Address alignment.


In these instructions:

  • Rn must not be PC.

  • Rm must not be SP and must not be PC.

  • Rt can be SP only for word loads and word stores.

  • Rt can be PC only for word loads.

When Rt is PC in a word load instruction:

  • Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address.

  • If the instruction is conditional, it must be the last instruction in the IT block.

Condition flags

These instructions do not change the flags.


    STR    R0, [R5, R1]         ; Store value of R0 into an address equal to
                                ; sum of R5 and R1.
    LDRSB  R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
                                ; sum of R5 and two times R1, sign extended it
                                ; to a word value and put it in R0.
    STR    R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
                                ; and four times R2.
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