4.5.2. Cache Type Register

The CTR provides information about the cache architecture. See the register summary in Table 4.39 for its attributes. The bit assignments are:

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Table 4.41. CTR bit assignments

BitsNameDescription
[31:29]Format

Register format:

0b100

Armv7 register format.

[28]-Reserved, RAZ.
[27:24]CWG

Cache Writeback Granule:

0b0011

8 word granularity for the Cortex-M7 processor.

[23:20]ERG

Exclusives Reservation Granule:

0b0000

The local monitor within the processor does not hold any physical address. It treats any STREX instruction access as matching the address of the previous LDREX instruction. This means that the implemented exclusive reservation granule is the entire memory address range.

[19:16]DMinLine

Smallest cache line of all the data and unified caches under the core control:

0b0011

8 words for the Cortex-M7 processor.

[15:14]-All bits RAO.
[13:4]-Reserved, RAZ.
[3:0]IminLine

Smallest cache line of all the instruction caches under the control of the processor:

0b0011

8 words for the Cortex-M7 processor.


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