4.8.7. Cache maintenance design hints and tips

You must always place a DSB and ISB instruction sequence after a cache maintenance operation to ensure that the effect is observed by any following instructions in the software.

When using a cache maintenance operation by address or set/way a DSB instruction must be executed after any previous load or store, and before the maintenance operation, to guarantee that the effect of the load or store is observed by the operation. For example, if a store writes to the address accessed by a DCCMVAC the DSB instruction guarantees that the dirty data is correctly cleaned from the data cache.

When one or more maintenance operations have been executed, use of a DSB instruction guarantees that they have completed and that any following load or store operations executes in order after the maintenance operations.

Cache maintenance operations always complete in-order with respect to each other. This means only one DSB instruction is required to guarantee the completion of a set of maintenance operations.

The following code sequence shows how to use cache maintenance operations to synchronize the data and instruction caches for self-modifying code. The sequence is entered with <Rx> containing the new 32-bit instruction. Use STRH in the first line instead of STR for a 16-bit instruction:

STR <Rx>, <inst_address1>
DSB                           ; Ensure the data has been written to the cache.
STR <inst_address1>, DCCMVAU  ; Clean data cache by MVA to point of unification (PoU).STR <inst_address1>, ICIMVAU  ; Invalidate instruction cache by MVA to PoU.DSB                           ; Ensure completion of the invalidations.ISB                           ; Synchronize fetched instruction stream.
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