4.7. Floating Point Unit

This section describes the optional Floating-Point Unit (FPU) in a Cortex-M7 device. The FPU implements the FPv5 floating-point extensions.

Depending on your implementation, the FPU fully supports either single-precision, or double-precision, or both for add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.

The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.

For implementations with the FPU configured for single-precision only, the FPU contains 32 single-precision extension registers, that you can also access as 16 doubleword registers for load, store, and move operations.

Table 4.58 shows the floating-point system registers in the Cortex-M7 processor with FPU.

Table 4.58. Cortex-M7 floating-point system registers

AddressNameType

Required

privilege

ResetDescription
0xE000ED88CPACRRWPrivileged0x00000000Coprocessor Access Control Register
0xE000EF34FPCCRRWPrivileged0xC0000000Floating-point Context Control Register
0xE000EF38FPCARRWPrivileged-Floating-point Context Address Register
-FPSCR[a]RWUnprivileged-Floating-point Status Control Register
0xE000EF3CFPDSCRRWPrivileged0x00000000Floating-point Default Status Control Register

[a] The FPSCR register is not memory-mapped, it can be accessed using the VMSR and VMRS instructions, see VMRS and VMSR. Software can only access the FPSCR when the FPU is enabled, see Enabling the FPU.


The following sections describe the floating-point system registers whose implementation is specific to this processor.

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