2.2.6. Synchronization primitives

The instruction set support for the Cortex-M7 processor includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.

A pair of synchronization primitives comprises:

A Load-Exclusive instruction

Used to read the value of a memory location, requesting exclusive access to that location.

A Store-Exclusive instruction

Used to attempt to write to the same memory location, returning a status bit to a register. If this bit is:

0

it indicates that the thread or process gained exclusive access to the memory, and the write succeeds,

1

it indicates that the thread or process did not gain exclusive access to the memory, and no write was performed.

The pairs of Load-Exclusive and Store-Exclusive instructions are:

Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.

To perform an exclusive read-modify-write of a memory location, software must:

  1. Use a Load-Exclusive instruction to read the value of the location.

  2. Modify the value, as required.

  3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.

  4. Test the returned status bit. If this bit is:

    0

    The read-modify-write completed successfully.

    1

    No write was performed. This indicates that the value returned at step 1 might be out of date. The software must retry the entire read-modify-write sequence.

Software can use the synchronization primitives to implement a semaphore as follows:

  1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free.

  2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address.

  3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1.

The Cortex-M7 processor includes an exclusive access monitor, that tags the fact that the processor has executed a Load-Exclusive instruction. If the processor is part of a multiprocessor system and the address is in a shared region of memory, the system also globally tags the memory locations addressed by exclusive accesses by each processor.

The processor removes its exclusive access tag if:

In a multiprocessor implementation:

For more information about the synchronization primitive instructions, see LDREX and STREX and CLREX.

Copyright © 2015, 2018 Arm. All rights reserved.ARM DUI 0646C
Non-ConfidentialID121118