4.9.2. AHBP Control Register

Note

This register is optional and might not be available in your implementation.

Depending on your implementation, the AHBPCR controls accesses to the device either on the AHBP interface or AXI master interface. The bit assignments are:

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Table 4.70. AHBPCR bit assignments

BitsNameTypeFunction
[31:4]--Reserved, RAZ/WI.
[3:1]SZRO

AHBP size. The values that apply depend on your implementation:

0b001

64MB.

0b010

128MB.

0b011

256MB.

0b100

512MB.

[0]ENRW

AHBP enable:

0

AHBP disabled. When disabled all accesses are made to the AXI master.

1

AHBP enabled.


Enabling the AHBP interface

Depending on your implementation, the AHBP interface can be enabled at reset in the system by an external signal on the processor. If it is disabled at reset then the following code example can be used to enable the AHPB interface from software:

AHBPCR  EQU 0xE000EF98        LDR r11, =AHBPCR        LDR r0, [r11]        ORR r0, r0, #0x1         ; Set AHBPCR.EN field        STR r0, [r11]        DSB        ISB
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