A.1. Cortex-M7 processor options

Table A.1 shows the Cortex-M7 processor implementation options.

Table A.1. Effects of the Cortex-M7 processor implementation options

OptionDescription, and affected documentation
RTL version

The RTL version can affect the availability of some features. This affects:

Inclusion of MPU

The implementer decides whether to include the Memory Protection Unit (MPU). This affects references to the MPU, or MPU registers in:

The MPU can be implemented either as an 8-region MPU or a 16-region MPU. This affects the DREGION bits in the MPU_TYPE register.

Inclusion of FPU

The implementer decides whether to include the Floating-Point Unit (FPU). The FPU implemented can be a single-precision only FPU, or single-precision and double-precision FPU. This affects:

Number of interrupts

The implementer decides how many interrupts the Cortex-M7 processor implementation supports, in the range 1-240. This affects:

Number of priority bits

The implementer decides how many priority bits are implemented in priority value fields, in the range 3-8. Register priority value fields are 8 bits wide, and un-implemented low-order bits read as zero and ignore writes. This affects:

Inclusion of the WIC 

The implementer decides whether to include the Wakeup Interrupt Controller (WIC). This affects:

Sleep mode power-saving

The implementer decides what power-saving sleep modes to implement, see Power management.

Sleep mode power saving might also affect SysTick behavior, see SysTick design hints and tips.

Register reset values 

The implementer decides whether all registers in the register bank can be reset. This affects the reset values in Table 2.2.


The implementer decides whether the memory system is little-endian or big-endian, and depends on the external signal, CFGBIGEND, see Data types, Memory endianness and ENDIANNESS bit in Table 4.17.

Memory features

Some features of the memory system are implementation specific. This affects details of vendor-specific memory in Memory model, including:

  • The figure in that section. The memory map configuration of the Code SRAM and peripheral memory region 0x00000000 to 0x5FFFFFFF to any implemented TCM and system space.

  • Information in Table 2.11.

  • The additional memory attributes available.

  • Information in Table 2.12.

The implementer decides whether to include caches. This affects references to caches or cache registers in:

The implementer decides whether to include Tightly-Coupled Memories (TCMs). This affects references to Tightly-Coupled Memory (TCM) and registers in:

SysTick SYST_CALIB register

The implementation of this register is implementation defined. This affects:

VTOR.TBLOFF[31:7] vector base address

The initial value in the Vector Table Offset Register (VTOR), which controls the vector base address, is implementation defined, and depends on the external signal, INITVTOR. This affects the configuration of the TBLOFF[31:7] bit field in Table 4.16. This also affects the address from where the processor loads:

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