2.3.4. Vector table

The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 2.1 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code, see Thumb state.

Figure 2.1. Vector table

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Note

Figure 2.1 shows the maximum range of values for the exception number, IRQ number, offset and vector. The actual range of values available is implementation defined.

On system reset, the vector table is at the address configured at implementation, typically 0x00000000. Privileged software can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000000-0xFFFFFF80. The silicon vendor must configure the top range value, that depends on the number of interrupts implemented. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64, see Vector Table Offset Register.

Arm recommends that you locate the vector table in either the CODE, SRAM, External RAM, or External Device areas of the system memory map, see Memory model. Using the Peripheral, Private peripheral bus, or Vendor-specific memory areas can lead to unpredictable behavior in some systems. This is because the processor uses different interfaces for load/store instructions and vector fetch in these memory areas. If the vector table is located in a region of memory that is cacheable, you must treat any load or store to the vector as self-modifying code and use cache maintenance instructions to synchronize the update to the data and instruction caches, see Cache maintenance design hints and tips.

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