4.8. Cache maintenance operations

Note

Ignore this section if caches are not present in your implementation.

This section describes the optional cache maintenance registers in a Cortex-M7 device. These registers control the data and instruction cache.

The operations supported for the instruction cache and data cache are:

The cache maintenance operations are only accessible by privileged loads and stores. Unprivileged accesses to these registers always generate a BusFault.

Table 4.64. Cache Maintenance Space register summary

AddressName Type

Required

privilege

Reset

value

Description
0xE000EF50ICIALLUWOPrivileged

Unknown

Instruction cache invalidate all to the Point of Unification (PoU)[a]

0xE000EF54----Reserved
0xE000EF58ICIMVAUWOPrivileged

Unknown

Instruction cache invalidate by address to the PoU[a]

0xE000EF5CDCIMVACWOPrivileged

Unknown

Data cache invalidate by address to the Point of Coherency (PoC)[b]

0xE000EF60DCISWWOPrivileged

Unknown

Data cache invalidate by set/way

0xE000EF64DCCMVAUWOPrivileged

Unknown

Data cache clean by address to the PoU[a]

0xE000EF68DCCMVACWOPrivileged

Unknown

Data cache clean by address to the PoC[b]
0xE000EF6CDCCSWWOPrivileged

Unknown

Data cache clean by set/way

0xE000EF70DCCIMVACWOPrivileged

Unknown

Data cache clean and invalidate by address to the PoC[b]

0xE000EF74DCCISWWOPrivileged

Unknown

Data cache clean and invalidate by set/way

0xE000EF78BPIALLRAZ/WIPrivileged-

The BPIALL register is not implemented

[a] Cache maintenance operations by PoU can be used to synchronize data between the Cortex-M7 data and instruction Caches, for example when the software uses self-modifying code.

[b] Cache maintenance operations by PoC can be used to synchronize data between the Cortex-M7 data cache and an external agent such as a system DMA.


Copyright © 2015, 2018 Arm. All rights reserved.ARM DUI 0646C
Non-ConfidentialID121118