### 3.6.11. UMULL, UMLAL, SMULL, and SMLAL

Signed and Unsigned Multiply Long, with optional Accumulate,
using 32‑bit operands and producing a 64‑bit result.

`op`

{`cond`

} `RdLo`

, `RdHi`

, `Rn`

, `Rm`

Where:

`op`

Is one of:

`UMULL`

`UMLAL`

Unsigned
Multiply, with Accumulate Long.

`SMULL`

`SMLAL`

Signed
Multiply, with Accumulate Long.

`cond`

`RdHi`

, `RdLo`

Are the destination registers. For `UMLAL`

and `SMLAL`

they
also hold the accumulating value of the lower and upper words respectively.

`Rn, Rm`

Are registers holding the operands.

The `UMULL`

instruction interprets the values from `Rn`

and `Rm`

as
unsigned integers. It multiplies these integers and places the least
significant 32 bits of the result in `RdLo`

,
and the most significant 32 bits of the result in `RdHi`

.

The `UMLAL`

instruction interprets the values from `Rn`

and `Rm`

as
unsigned integers. It multiplies these integers, adds the 64‑bit
result to the 64‑bit unsigned integer contained in `RdHi`

and `RdLo`

, and
writes the result back to `RdHi`

and `RdLo`

.

The `SMULL`

instruction interprets the values from `Rn`

and `Rm`

as
two’s complement signed integers. It multiplies these integers and
places the least significant 32 bits of the result in `RdLo`

,
and the most significant 32 bits of the result in `RdHi`

.

The `SMLAL`

instruction interprets the values from `Rn`

and `Rm`

as
two’s complement signed integers. It multiplies these integers,
adds the 64‑bit result to the 64‑bit signed integer contained in `RdHi`

and `RdLo`

,
and writes the result back to `RdHi`

and `RdLo`

.

These instructions do not affect the condition code flags.

UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 × R6
SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 × R8