### 3.5.3. ASR, LSL, LSR, ROR, and RRX

Arithmetic Shift Right, Logical Shift Left, Logical Shift
Right, Rotate Right, and Rotate Right with Extend.

`op`

{S}{`cond`

} `Rd`

, `Rm`

, `Rs`

`op`

{S}{`cond`

} `Rd`

, `Rm`

, #`n`

RRX{S}{`cond`

} `Rd`

, `Rm`

Where:

`op`

`S`

Is
an optional suffix. If `S`

is specified, the
condition code flags are updated on the result of the operation,
see *Conditional execution*.

`Rd`

Is the destination register.

`Rm`

Is the register holding the value to be shifted.

`Rs`

Is the register holding the shift length to apply
to the value in `Rm`

.
Only the least significant byte is used and can be in the range
0-255.

`n`

Is the shift length. The range of shift length depends
on the instruction:

`ASR`

Shift length from 1
to 32

`LSL`

Shift
length from 0 to 31

`LSR`

Shift
length from 1 to 32

`ROR`

Shift
length from 1 to 31.

### Note

`MOVS ``Rd`

, `Rm`

is
the preferred syntax for `LSLS ``Rd`

, `Rm`

, `#0`

.

`ASR`

, `LSL`

, `LSR`

, and `ROR`

move
the bits in the register `Rm`

to
the left or right by the number of places specified by constant `n`

or
register `Rs`

.

`RRX`

moves the bits in register `Rm`

to
the right by 1.

In all these instructions, the result is written to `Rd`

,
but the value in register `Rm`

remains unchanged.
For details on what result is generated by the different instructions,
see *Shift Operations*.

Do not use SP and do not use PC.

If `S`

is specified:

These instructions update the N, Z and C flags according to
the result.

The C flag is updated to the last bit shifted out,
except when the shift length is 0, see *Shift Operations*.

ASR R7, R8, #9 ; Arithmetic shift right by 9 bits.
LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update.
LSR R4, R5, #6 ; Logical shift right by 6 bits.
ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6.
RRX R4, R5 ; Rotate right with extend.