3.4.2. LDR and STR, immediate offset

Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.

Syntax

op{type}{cond} Rt, [Rn {, #offset}]        ; immediate offset
op{type}{cond} Rt, [Rn, #offset]!          ; pre-indexed
op{type}{cond} Rt, [Rn], #offset           ; post-indexed
opD{cond} Rt, Rt2, [Rn {, #offset}]        ; immediate offset, two words
opD{cond} Rt, Rt2, [Rn, #offset]!          ; pre-indexed, two words
opD{cond} Rt, Rt2, [Rn], #offset           ; post-indexed, two words

Where:

op

Is one of:

LDR

Load Register.

STR

Store Register.

type

Is one of:

B

Unsigned byte, zero extend to 32 bits on loads.

SB

Signed byte, sign extend to 32 bits (LDR only).

H

Unsigned halfword, zero extend to 32 bits on loads.

SH

Signed halfword, sign extend to 32 bits (LDR only).

Omit, for word.

cond

Is an optional condition code. See Conditional execution.

Rt

Is the register to load or store.

Rn

Is the register on which the memory address is based.

offset

Is an offset from Rn. If offset is omitted, the address is the contents of Rn.

Rt2

Is the additional register to load or store for two-word operations.

Operation

LDR instructions load one or two registers with a value from memory.

STR instructions store one or two register values to memory.

Load and store instructions with immediate offset can use the following addressing modes:

Offset addressing

The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is:

[Rn, #offset]
Pre-indexed addressing

The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is:

[Rn, #offset]!
Post-indexed addressing

The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is:

[Rn], #offset

The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned. See Address alignment.

Table 3.6 shows the ranges of offset for immediate, pre-indexed and post-indexed forms.

Table 3.6. Offset ranges

Instruction typeImmediate offsetPre-indexedPost-indexed
Word, halfword, signed halfword, byte, or signed byte−255 to 4095−255 to 255−255 to 255
Two wordsmultiple of 4 in the range −1020 to 1020 multiple of 4 in the range −1020 to 1020 multiple of 4 in the range −1020 to 1020

Restrictions

For load instructions:

  • Rt can be SP or PC for word loads only.

  • Rt must be different from Rt2 for two-word loads.

  • Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

When Rt is PC in a word load instruction:

  • Bit[0] of the loaded value must be 1 for correct execution.

  • A branch occurs to the address created by changing bit[0] of the loaded value to 0.

  • If the instruction is conditional, it must be the last instruction in the IT block.

For store instructions:

  • Rt can be SP for word stores only.

  • Rt must not be PC.

  • Rn must not be PC.

  • Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

Condition flags

These instructions do not change the flags.

Examples

    LDR     R8, [R10]              ; Loads R8 from the address in R10.
    LDRNE   R2, [R5, #960]!        ; Loads (conditionally) R2 from a word
                                   ; 960 bytes above the address in R5, and
                                   ; increments R5 by 960.
    STR     R2, [R9,#const‑struc]  ; const‑struc is an expression evaluating
                                   ; to a constant in the range 0‑4095.
    STRH    R3, [R4], #4           ; Store R3 as halfword data into address in
                                   ; R4, then increment R4 by 4.
    LDRD    R8, R9, [R3, #0x20]    ; Load R8 from a word 32 bytes above the
                                   ; address in R3, and load R9 from a word 36
                                   ; bytes above the address in R3.
    STRD    R0, R1, [R8], #-16     ; Store R0 to address in R8, and store R1 to
                                   ; a word 4 bytes above the address in R8, 
                                   ; and then decrement R8 by 16.
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