4.9.3. L1 Cache Control Register

Note

This register is optional and might not be available in your implementation.

The CACR controls the optional L1 ECC and the L1 cache coherency usage model. The bit assignments are:

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Table 4.71. CACR bit assignments

BitsNameTypeFunction
[31:3]--Reserved, RAZ/WI.
[2]FORCEWTRW

Enables Force Write-Through in the data cache:

0

Disables Force Write-Through.

1

Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through.

This bit is RAZ/WI if the data cache is excluded. If the data cache is included the reset value of FORCEWT is 0.

[1]ECCDISRW

Enables ECC in the instruction and data cache:

0

Enables ECC in the instruction and data cache. This is RAO/WI if both data cache and instruction cache are excluded or if ECC is excluded.

1

Disables ECC in the instruction and data cache. This is RAZ/WI if data cache is not configured.

[0]SIWTRW

Shared cacheable-is-WT for data cache. Enables cache coherency usage:

0

Normal Cacheable Shareable locations are treated as being Non-cacheable. Programmed inner cacheability attributes are ignored. This is the default mode of operation for shared memory. The data cache is transparent to software for these locations and therefore no software maintenance is required to maintain coherency.

1

Normal Cacheable Shareable locations are treated as Write-Through. Programmed inner cacheability attributes are ignored. All writes are globally visible. Other memory agent updates are not visible to Cortex-M7 processor software without suitable cache maintenance.

Useful for heterogeneous MP-systems where, for example, the Cortex-M7 processor is integrated on the Accelerator Coherency Port (ACP) interface on an MP-capable processor.

This bit is RAZ/WI when data cache is not configured.


Disabling cache error checking and correction

If cache error checking and correction is included in the processor it is enabled by default from reset. The following code example can be used to disable the feature. The operation is carried out by modifying the CACR.ECCEN field in the PPB memory region.

CACR    EQU 0xE000EF9C        LDR r11, =CACR        LDR r0, [r11]        BFS r0, #0x1, #0x1    ; Clear CACR.ECCEN        STR r0, [r11]                        DSB        ISB

Care must be taken when software changes CACR.ECCEN. If CACR.ECCEN changes when the caches contain data, ECC information in the caches might not be correct for the new setting, resulting in unexpected errors and data loss. Therefore software must only change CACR.ECCEN when both caches are turned off and both caches must be invalidated after the change.

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