4.6. Optional Memory Protection Unit

This section describes the optional Memory Protection Unit (MPU).

The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports:

The memory attributes affect the behavior of memory accesses to the region. The Cortex-M7 MPU defines:

When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7.

The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only.

The Cortex-M7 MPU memory map is unified. This means instruction accesses and data accesses have same region settings.

If a program accesses a memory location that is prohibited by the MPU, the processor generates a MemManage fault. This causes a fault exception, and might cause termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.

Configuration of MPU regions is based on memory types, see Memory regions, types and attributes.

Table 4.47 shows the possible MPU region attributes. These include Shareability and cache behavior attributes that are generally only relevant when the processor is configured with caches.

Table 4.47. Memory attributes summary

Memory typeShareabilityOther attributesDescription
Strongly Ordered--All accesses to Strongly-Ordered Memory occur in program order. All Strongly-Ordered regions are assumed to be shared.
DeviceShared-Memory-mapped peripherals that several processors share.
 Non-shared-Memory-mapped peripherals that only a single processor uses.
NormalSharedNon-cacheable Write-Through Cacheable Write-Back CacheableNormal memory that is shared between several processors.
 Non-sharedNon-cacheable Write-Through Cacheable Write-Back CacheableNormal memory that only a single processor uses.

Use the MPU registers to define the MPU regions and their attributes. The MPU registers are:

Table 4.48. MPU registers summary

AddressName Type

Required

privilege

Reset

value

Description
0xE000ED90MPU_TYPEROPrivileged

0x00000800

MPU Type Register
0xE000ED94MPU_CTRLRWPrivileged0x00000000MPU Control Register
0xE000ED98MPU_RNRRWPrivilegedUnknown MPU Region Number Register
0xE000ED9CMPU_RBARRWPrivilegedUnknown MPU Region Base Address Register
0xE000EDA0MPU_RASRRWPrivileged-[a]MPU Region Attribute and Size Register
0xE000EDA4MPU_RBAR_A1RWPrivilegedUnknownAlias of RBAR, see MPU Region Base Address Register
0xE000EDA8MPU_RASR_A1RWPrivileged-[a]Alias of RASR, see MPU Region Attribute and Size Register
0xE000EDACMPU_RBAR_A2RWPrivilegedUnknownAlias of RBAR, see MPU Region Base Address Register
0xE000EDB0MPU_RASR_A2RWPrivileged-[a]Alias of RASR, see MPU Region Attribute and Size Register
0xE000EDB4MPU_RBAR_A3RWPrivilegedUnknownAlias of RBAR, see MPU Region Base Address Register
0xE000EDB8MPU_RASR_A3RWPrivileged-[a]Alias of RASR, see MPU Region Attribute and Size Register

[a] Unknown apart from the ENABLE field, which is reset to 0.


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