4.4.1. SysTick Control and Status Register

The SysTick SYST_CSR register enables the SysTick features. See the register summary in Table 4.33 for its attributes. The bit assignments are:

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Table 4.34. SysTick SYST_CSR bit assignments


Returns 1 if timer counted to 0 since last time this was read.


Indicates the clock source:


External clock.


Processor clock.


Enables SysTick exception request:


Counting down to zero does not assert the SysTick exception request.


Counting down to zero asserts the SysTick exception request.

Software can use COUNTFLAG to determine if SysTick has ever counted to zero.


Enables the counter:


Counter disabled.


Counter enabled.

When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR register and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then loads the RELOAD value again, and begins counting.

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