4.3.7. Configuration and Control Register

The CCR controls entry to Thread mode and enables:

See the register summary in Table 4.12 for the CCR attributes.

The bit assignments are:

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Table 4.20. CCR bit assignments

BitsNameTypeFunction
[31:19]--Reserved.
[18]BPRO

Always reads-as-one. It indicates branch prediction is enabled.

[17]ICRW

Enables L1 instruction cache. This bit is optional:

0

L1 instruction cache disabled.

1

L1 instruction cache enabled.

[16]DCRW

Enables L1data cache. This bit is optional:

0

L1 data cache disabled.

1

L1 data cache enabled.

[15:10]--Reserved.
[9]STKALIGNRO

Always reads-as-one. It indicates stack alignment on exception entry is 8-byte aligned.

On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.

[8]BFHFNMIGNRW

Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the hard fault, NMI, and FAULTMASK escalated handlers:

0

Data bus faults caused by load and store instructions cause a lock-up.

1

Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.

Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them.

[7:5]--Reserved.
[4]DIV_0_TRPRW

Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:

0

Do not trap divide by 0.

1

Trap divide by 0.

When this bit is set to 0, a divide by zero returns a quotient of 0.

[3]UNALIGN_TRPRW

Enables unaligned access traps:

0

Do not trap unaligned halfword and word accesses.

1

Trap unaligned halfword and word accesses.

If this bit is set to 1, an unaligned access generates a UsageFault.

Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.

[2]--Reserved.
[1]USERSETMPENDRW

Enables unprivileged software access to the STIR, see Software Trigger Interrupt Register:

0

Disable.

1

Enable.

[0]NONBASETHRDENARW

Indicates how the processor enters Thread mode:

0

Processor can enter Thread mode only when no exception is active.

1

Processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception return.


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