2.1.3. Core registers

The processor core registers are:

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 2.2. Core register set summary

NameType [a]Required privilege [b]

Reset value

Description
R0-R12RWEitherUnknownGeneral-purpose registers
MSPRWEitherSee descriptionStack Pointer
PSPRWEitherUnknownStack Pointer
LRRWEither0xFFFFFFFFLink Register
PCRWEitherSee descriptionProgram Counter
PSRRWEither0x01000000[c] Program Status Register
ASPRRWEitherUnknownApplication Program Status Register
IPSRROPrivileged0x00000000Interrupt Program Status Register
EPSRROPrivileged0x01000000[c]Execution Program Status Register
PRIMASKRWPrivileged0x00000000Priority Mask Register
FAULTMASKRWPrivileged0x00000000Fault Mask Register
BASEPRIRWPrivileged0x00000000Base Priority Mask Register
CONTROLRWPrivileged0x00000000CONTROL register

[a] Describes access type during program execution in thread mode and Handler mode. Debug access can differ.

[b] An entry of Either means privileged and unprivileged software can access the register.

[c] The EPSR reads as zero when executing an MRS instruction.


General-purpose registers

R0-R12 are 32-bit general-purpose registers for data operations.

Stack Pointer

The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use:

0

Main Stack Pointer (MSP). This is the reset value.

1

Process Stack Pointer (PSP).

On reset, the processor loads the MSP with the value from the implementation-defined address 0x00000000.

Link Register

The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor sets the LR value to 0xFFFFFFFF.

Program Counter

The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at the initial value of the Vector Table Offset Register (VTOR) plus 0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.

See Vector Table Offset Register for more information.

Program Status Register

The Program Status Register (PSR) combines:

  • Application Program Status Register (APSR).

  • Interrupt Program Status Register (IPSR).

  • Execution Program Status Register (EPSR).

These registers are mutually exclusive bit fields in the 32-bit PSR. The bit assignments are:

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example:

  • Read all the registers using PSR with the MRS instruction.

  • Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.

The PSR combinations and attributes are:

Table 2.3. PSR register combinations

RegisterTypeCombination
PSRRW[a], [b]APSR, EPSR, and IPSR
IEPSRRO[b]EPSR and IPSR
IAPSRRW[a]APSR and IPSR
EAPSRRW[b]APSR and EPSR

[a] The processor ignores writes to the IPSR bits.

[b] Reads of the EPSR bits return zero, and the processor ignores writes to these bits


See the instruction descriptions MRS and MSR for more information about how to access the program status registers.

Application Program Status Register

The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 2.2 for its attributes. The bit assignments are:

Table 2.4. APSR bit assignments

BitsNameFunction
[31]N

Negative flag.

[30]Z

Zero flag.

[29]C

Carry or borrow flag.

[28]V

Overflow flag.

[27]QDSP overflow and saturation flag.
[26:20]-Reserved.
[19:16]GE[3:0]Greater than or Equal flags. See SEL for more information.
[15:0]-Reserved.

Interrupt Program Status Register

The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 2.2 for its attributes. The bit assignments are:

Table 2.5. IPSR bit assignments

BitsNameFunction
[31:9]-Reserved.
[8:0]ISR_NUMBER

This is the number of the current exception:

0

Thread mode.

1

Reserved.

2

NMI.

3

HardFault.

4

MemManage.

5

BusFault.

6

UsageFault.

7-10

Reserved.

11

SVCall.

12

Reserved for Debug.

13

Reserved.

14

PendSV.

15

SysTick.

16

IRQ0.

.

.

.

.

.

.

255

IRQ239[a].

See Exception types for more information.

[a] This is the maximum number of exceptions. The actual maximum number of exceptions available is implementation defined.


Execution Program Status Register

The EPSR contains the Thumb state bit, and the execution state bits for either the:

  • If-Then (IT) instruction.

  • Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.

See the register summary in Table 2.2 for the EPSR attributes. The bit assignments are:

Table 2.6. EPSR bit assignments

BitsNameFunction
[31:27]-Reserved
[26:25], [15:10]ICI

Interruptible-continuable instruction bits, see Interruptible-continuable instructions

[26:25], [15:10]IT

Indicates the execution state bits of the IT instruction, see IT

[24]T

Thumb state bit, see Thumb state

[23:16]-Reserved
[9:0]-Reserved

Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are ignored.

Interruptible-continuable instructions

When an interrupt occurs during the execution of an LDM, STM, PUSH or POP instruction, and when an FPU is implemented an VLDM, VSTM, VPUSH, or VPOP instruction, the processor:

  • Stops the load multiple or store multiple instruction operation temporarily.

  • Stores the next register operand in the multiple operation to EPSR bits[15:12].

After servicing the interrupt, the processor:

  • Returns to the register pointed to by bits[15:12].

  • Resumes execution of the multiple load or store instruction.

When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.

If-Then block

The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See IT for more information.

Thumb state

The Cortex-M7 processor only supports execution of instructions in Thumb state. The following can clear the T bit to 0:

  • Instructions BLX, BX, LDR pc, [], and POP{PC}.

  • Restoration from the stacked xPSR value on an exception return.

  • Bit[0] of the vector value on an exception entry or reset.

Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See Lockup for more information.

Exception mask registers

The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might affect timing critical tasks.

To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See MRS, MSR, and CPS for more information.

Priority Mask Register

The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 2.2 for its attributes. The bit assignments are:

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 2.7. PRIMASK register bit assignments

BitsNameFunction
[31:1]-Reserved.
[0]PRIMASK
0

No effect.

1

Prevents the activation of all exceptions with configurable priority.


Fault Mask Register

The FAULTMASK register prevents activation of all exceptions except for non-maskable interrupt. See the register summary in Table 2.2 for its attributes. The bit assignments are:

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 2.8. FAULTMASK register bit assignments

BitsNameFunction
[31:1]-Reserved.
[0]FAULTMASK
0

No effect.

1

Prevents the activation of all exceptions except for NMI.


The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.

Base Priority Mask Register

The BASEPRI register defines the minimum group priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower group priority level as the BASEPRI value. See the register summary in Table 2.2 for its attributes. The bit assignments are:

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 2.9. BASEPRI register bit assignments

BitsNameFunction
[31:8]-Reserved.
[7:0]BASEPRI [a]

Priority mask bits:

0x00

No effect.

Nonzero

Defines the base priority for exception processing.

The processor does not process any exception with a priority value greater than or equal to BASEPRI.

[a] This field is similar to the priority fields in the interrupt priority registers. Only bits[7:M] of this field are implemented, and bits[M-x:0] read as zero and ignore writes. The values of M and x are implementation defined. See Interrupt Priority Registers for more information. Remember that higher priority field values correspond to lower exception priorities.


CONTROL register

The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode, and if implemented, indicates whether the FPU state is active. See the register summary in Table 2.2 for its attributes. The bit assignments are:

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 2.10. CONTROL register bit assignments

BitsNameFunction
[31:3]-Reserved.
[2]FPCA

When floating-point is implemented this bit indicates whether floating-point context is active:

0

No floating-point context active.

1

Floating-point context active.

This bit is used to determine whether to preserve floating-point state when processing an exception.

[1]SPSEL

Defines the currently active stack pointer:

0

MSP is the current stack pointer.

1

PSP is the current stack pointer.

In Handler mode this bit reads as zero and ignores writes. The Cortex-M7 processor updates this bit automatically on exception return.

[0]nPRIV

Defines the Thread mode privilege level:

0

Privileged.

1

Unprivileged.


Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value, see Table 2.15.

In an OS environment, the vendor recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.

By default, Thread mode uses the MSP. To switch the stack pointer that is used in Thread mode to the PSP, either:

  • Use the MSR instruction to set the CONTROL.SPSEL bit, the current active stack pointer bit, to 1, see MSR.

  • Perform an exception return to Thread mode with the appropriate EXC_RETURN value, see Table 2.15.

Note

When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB instruction execute using the new stack pointer. See ISB.

Copyright © 2015, 2018 Arm. All rights reserved.ARM DUI 0646C
Non-ConfidentialID121118