3.11.10. VLDM

Floating-point Load Multiple.

Syntax

VLDM{mode}{cond}{.size} Rn{!}, list

Where:

mode

Is the addressing mode:

IA

Increment after. The consecutive addresses start at the address specified in Rn.

DB

Decrement before. The consecutive addresses end before

the address specified in Rn.

cond

Is an optional condition code. See Conditional execution.

size

Is an optional data size specifier.

Rn

Is the base register. The SP can be used.

!

Is the command to the instruction to write a modified value back to Rn. This is required if mode == DB, and is optional if mode == IA.

list

Is the list of extension registers to be loaded, as a list of consecutively numbered doubleword or singleword registers, separated by commas and surrounded by brackets.

Operation

This instruction loads multiple extension registers from consecutive memory locations using an address from an Arm core register as the base address.

Restrictions

The restrictions are:

  • If size is present, it must be equal to the size in bits, 32 or 64, of the registers in list.

  • For the base address, the SP can be used. In the Arm instruction set, if ! is not specified the PC can be used.

  • list must contain at least one register. If it contains doubleword registers, it must not contain more than 16 registers.

  • If using the Decrement before addressing mode, the write back flag, !, must be appended to the base register specification.

Condition flags

These instructions do not change the flags.

Example

VLDMIA.F64 r1, {d3,d4,d5}

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