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Home > The Cortex-M7 Instruction Set > Multiply and divide instructions > SMLSD and SMLSLD |

Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual.

{X}`op`

{}`cond`

,`Rd`

,`Rn`

,`Rm`

;`Ra`

`SMLSD`

{X}{`op`

}`cond`

,`RdLo`

,`RdHi`

,`Rn`

;`Rm`

`SMLSLD`

Where:

`op`

Is one of:

`SMLSD`

Signed Multiply Subtract Dual.

`SMLSDX`

Signed Multiply Subtract Dual reversed.

`SMLSLD`

Signed Multiply Subtract Long Dual.

`SMLSLDX`

Signed Multiply Subtract Long Dual reversed.

If

`X`

is present, the multiplications are bottom`×`

top and top`×`

bottom. If the`X`

is omitted, the multiplications are bottom`×`

bottom and top`×`

top.`cond`

Is an optional condition code. See

*Conditional execution*.`Rd`

Is the destination register.

`Rn, Rm`

Are registers holding the first and second operands.

`Ra`

Is the register holding the accumulate value.

`RdLo`

Supplies the lower 32 bits of the accumulate value, and is the destination register for the lower 32 bits of the result.

`RdHi`

Supplies the upper 32 bits of the accumulate value, and is the destination register for the upper 32 bits of the result.

The `SMLSD`

instruction interprets the values from
the first and second operands as four signed halfwords. This instruction:

Optionally rotates the halfwords of the second operand.

Performs two signed 16 × 16-bit halfword multiplications.

Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.

Adds the signed accumulate value to the result of the subtraction.

Writes the result of the addition to the destination register.

The `SMLSLD`

instruction interprets the values
from

and `Rn`

as
four signed halfwords.
This instruction:`Rm`

Optionally rotates the halfwords of the second operand.

Performs two signed 16 × 16-bit halfword multiplications.

Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.

Adds the 64-bit value in

and`RdHi`

to the result of the subtraction.`RdLo`

Writes the 64-bit result of the addition to the

and`RdHi`

.`RdLo`

The * SMLSD{X}* instruction sets the Q
flag if the accumulate operation overflows. Overflow cannot occur
during the multiplications or subtraction.

For the Thumb instruction set, these instructions do not affect the condition code flags.

SMLSD R0, R4, R5, R6 ; Multiplies bottom halfword of R4 with bottom

; halfword of R5, multiplies top halfword of R4

; with top halfword of R5, subtracts second from

; first, adds R6, writes to R0.

SMLSDX R1, R3, R2, R0 ; Multiplies bottom halfword of R3 with top

; halfword of R2, multiplies top halfword of R3

; with bottom halfword of R2, subtracts second from

; first, adds R0, writes to R1.

SMLSLD R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with bottom

; halfword of R2, multiplies top halfword of R6

; with top halfword of R2, subtracts second from

; first, adds R6:R3, writes to R6:R3.

SMLSLDX R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with top

; halfword of R2, multiplies top halfword of R6

; with bottom halfword of R2, subtracts second from

; first, adds R6:R3, writes to R6:R3.