3.11.19. VMOV Arm Core register to scalar

Transfers one word to a floating-point register from an Arm core register.

Syntax

VMOV{cond}{.32} Dd[x], Rt

Where:

cond

Is an optional condition code. See Conditional execution.

32

Is an optional data size specifier.

Dd[x]

Is the destination, where [x] defines which half of the doubleword is transferred, as follows:

  • If x is 0, the lower half is extracted.

  • If x is 1, the upper half is extracted.

Rt

Is the source Arm core register.

Operation

This instruction transfers one word to the upper or lower half of a doubleword floating-point register from an Arm core register.

Restrictions

Rt cannot be PC or SP.

Condition flags

These instructions do not change the flags.

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