3.11.15. VMOV Scalar to Arm Core register

Transfers one word of a doubleword floating-point register to an Arm core register.

Syntax

VMOV{cond} Rt, Dn[x]

Where:

cond

Is an optional condition code. See Conditional execution.

Rt

Is the destination Arm core register.

Dn

Is the 64-bit doubleword register.

x

Specifies which half of the doubleword register to use:

  • If x is 0, use lower half of doubleword register.

  • If x is 1, use upper half of doubleword register.

Operation

This instruction transfers one word from the upper or lower half of a doubleword floating-point register to an Arm core register.

Restrictions

Rt cannot be PC or SP.

Condition flags

These instructions do not change the flags.

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