1.1. About the Cortex-M7 processor and core peripherals

The Cortex-M7 processor is a high-performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:

Figure 1.1. Cortex-M7 processor implementation

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The Cortex-M7 processor is built on a high-performance processor core, with a 6-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The in-order superscalar processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design. It provides high-end processing hardware that includes a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division. It also provides optional single-precision, or both single-precision and double-precision, IEEE75-complaint floating-point computation.

To facilitate the design of cost-sensitive devices, the Cortex-M7 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M7 processor implements a version of the Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex-M7 processor instruction set provides the exceptional performance that is expected of a modern 32-bit architecture, with better code density than most 8-bit and 16-bit microcontrollers.

The Cortex-M7 processor closely integrates a configurable Nested Vectored Interrupt Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC includes a non-maskable interrupt (NMI), and can provide up to 256 interrupt priority levels for other interrupts. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes that includes an optional deep sleep function. This enables the entire device to be rapidly powered down while still retaining program state.

Reliability can be increased with optional automatic built-in fault detection and handling. With this option, the Cortex-M7 processor has Memory Built-in Self Test (MBIST) capability, and supports ECC (Error Correcting Code) on cache and TCM memories that enables SEC-DED (Single Error Correct, Double Error Detect) for accesses to memory. The Cortex-M7 processor is dual-redundant, which means it can operate in lock-step. The MCU vendor determines the reliability features configuration, therefore reliability features can differ across different devices and families.

To increase instruction throughput, the Cortex-M7 processor can execute certain pairs of instructions simultaneously. This is called dual issue.

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