3.6.3. SMLAWB, SMLAWT, SMLABB, SMLABT, SMLATB, and SMLATT

Signed Multiply Accumulate (halfwords).

Syntax

op{cond} Rd, Rn, Rm, Ra

Where:

op

Is one of:

SMLAWB

Signed Multiply Accumulate (word by halfword)

The bottom halfword, bits [15:0], of Rm is used.

SMLAWT

Signed Multiply Accumulate (word by halfword)

The top halfword, bits [31:16] of Rm is used.

SMLABB, SMLABT

Signed Multiply Accumulate Long (halfwords)

The bottom halfword, bits [15:0], of Rm is used.

SMLATB, SMLATT

Signed Multiply Accumulate Long (halfwords)

The top halfword, bits [31:16] of Rm is used.

cond

Is an optional condition code. See Conditional execution.

Rd

Is the destination register.

Rn, Rm

Are registers holding the values to be multiplied.

Ra

Is a register holding the value to be added or subtracted from.

Operation

The SMLABB, SMLABT, SMLATB, SMLATT instructions:

  • Multiply the specified signed halfword, top or bottom, values from Rn and Rm.

  • Add the value in Ra to the resulting 32-bit product.

  • Write the result of the multiplication and addition in Rd.

The non-specified halfwords of the source registers are ignored.

The SMLAWB and SMLAWT instructions:

  • Multiply the 32-bit signed values in Rn with:

    • The top signed halfword of Rm, T instruction suffix.

    • The bottom signed halfword of Rm, B instruction suffix.

  • Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product.

  • Write the result of the multiplication and addition in Rd.

The bottom 16 bits of the 48-bit product are ignored.

If overflow occurs during the addition of the accumulate value, the SMLAWB, SMLAWT, instruction sets the Q flag in the APSR. No overflow can occur during the multiplication.

Restrictions

In these instructions, do not use SP and do not use PC.

Condition flags

If an overflow is detected, the Q flag is set.

Examples

SMLABB  R5, R6, R4, R1  ; Multiplies bottom halfwords of R6 and R4, adds
                        ; R1 and writes to R5.
SMLATB  R5, R6, R4, R1  ; Multiplies top halfword of R6 with bottom halfword
                        ; of R4, adds R1 and writes to R5.
SMLATT  R5, R6, R4, R1  ; Multiplies top halfwords of R6 and R4, adds 
                        ; R1 and writes the sum to R5.
SMLABT  R5, R6, R4, R1  ; Multiplies bottom halfword of R6 with top halfword
                        ; of R4, adds R1 and writes to R5.
SMLABT  R4, R3, R2      ; Multiplies bottom halfword of R4 with top halfword of
                        ; R3, adds R2 and writes to R4.
SMLAWB  R10, R2, R5, R3 ; Multiplies R2 with bottom halfword of R5, adds
                        ; R3 to the result and writes top 32-bits to R10.
SMLAWT  R10, R2, R1, R5 ; Multiplies R2 with top halfword of R1, adds R5 
                        ; and writes top 32-bits to R10.
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