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Home > The Cortex-M7 Instruction Set > Floating-point instructions |

This section provides the instruction set that the single-precision and double-precision FPU uses.

Table 3.15 shows the floating-point instructions.

These instructions are only available if the FPU is included,
and enabled, in the system. See *Enabling the FPU* for information about enabling the floating-point
unit.

**Table 3.15. Floating-point instructions**

Mnemonic | Brief description | See |
---|---|---|

`VABS` | Floating-point Absolute | VABS |

`VADD` | Floating-point Add | VADD |

`VCMP` | Compare two floating-point registers, or one floating-point register and zero | VCMP and VCMPE |

`VCMPE` | Compare two floating-point registers, or one floating-point register and zero with Invalid Operation check | VCMP and VCMPE |

`VCVT` | Convert between floating-point and integer | VCVT and VCVTR between floating-point and integer |

`VCVT` | Convert between floating-point and fixed point | VCVT between floating-point and fixed-point |

`VCVTR` | Convert between floating-point and integer with rounding | VCVT and VCVTR between floating-point and integer |

`VCVTB` | Converts half-precision value to single-precision | VCVTB and VCVTT |

`VCVTT` | Converts single-precision register to half-precision | VCVTB and VCVTT |

`VDIV` | Floating-point Divide | VDIV |

`VFMA` | Floating-point Fused Multiply Accumulate | VFMA and VFMS |

`VFNMA` | Floating-point Fused Negate Multiply Accumulate | VFNMA and VFNMS |

`VFMS` | Floating-point Fused Multiply Subtract | VFMA and VFMS |

`VFNMS` | Floating-point Fused Negate Multiply Subtract | VFNMA and VFNMS |

`VLDM` | Load Multiple extension registers | VLDM |

`VLDR` | Loads an extension register from memory | VLDR |

`VMLA` | Floating-point Multiply Accumulate | VMLA and VMLS |

`VMLS` | Floating-point Multiply Subtract | VMLA and VMLS |

`VMOV` | Floating-point Move Immediate | VMOV Immediate |

`VMOV` | Floating-point Move Register | VMOV Register |

`VMOV` | Copy Arm core register to single-precision | VMOV Arm Core register to single-precision |

`VMOV` | Copy 2 Arm core registers to 2 single-precision | VMOV two Arm Core registers to two single-precision registers |

`VMOV` | Copies between Arm core register to scalar | VMOV Arm Core register to scalar |

`VMOV` | Copies between Scalar to Arm core register | VMOV Scalar to Arm Core register |

`VMRS` | Move to Arm core register from floating-point System Register | VMRS |

`VMSR` | Move to floating-point System Register from Arm Core register | VMSR |

`VMUL` | Multiply floating-point | VMUL |

`VNEG` | Floating-point negate | VNEG |

`VNMLA` | Floating-point multiply and add | VNMLA, VNMLS and VNMUL |

`VNMLS` | Floating-point multiply and subtract | VNMLA, VNMLS and VNMUL |

`VNMUL` | Floating-point multiply | VNMLA, VNMLS and VNMUL |

`VPOP` | Pop extension registers | VPOP |

`VPUSH` | Push extension registers | VPUSH |

`VSQRT` | Floating-point square root | VSQRT |

`VSTM` | Store Multiple extension registers | VSTM |

`VSTR` | Stores an extension register to memory | VSTR |

`VSUB` | Floating-point Subtract | VSUB |

`VSEL` | Select register, alternative to a pair of conditional `VMOV` | VSEL |

`VMAXNM` , `VMINNM` | Maximum, Minimum with IEEE754-2008 NaN handling | VMAXNM and VMINNM |

`VCVTA` , `VCVTN` , `VCVTP` , `VCVTM` | Float to integer conversion with directed rounding | VCVTA, VCVTN, VCVTP
and VCVTM |

`VRINTR` , `VRINTX` | Float to integer (in floating-point format) conversion | VRINTR and VRINTX |

`VRINTA` , `VRINTN` , `VRINTP` , `VRINTM` | Float to integer (in floating-point format) conversion with directed rounding | VRINTA, VRINTN, VRINTP,
VRINTM, and VRINTZ |