3.11.11. VLDR

Loads a single extension register from memory.

Syntax

VLDR{cond}{.F<32|64>} <Sd|Dd>, [Rn {, #imm}]
VLDR{cond}{.F<32|64>} <Sd|Dd>, label
VLDR{cond}{.F<32|64>} <Sd|Dd>, [PC, #imm]

Where:

cond

Is an optional condition code. See Conditional execution.

32, 64

Are the optional data size specifiers.

Dd

Is the destination register for a doubleword load.

Sd

Is the destination register for a singleword load.

Rn

Is the base register. The SP can be used.

imm

Is the + or - immediate offset used to form the address. Permitted address values are multiples of 4 in the range 0-1020.

label

Is the label of the literal data item to be loaded.

Operation

This instruction loads a single extension register from memory, using a base address from an Arm core register, with an optional offset.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

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