Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A

First release--

Table B.2. Differences between issue A and issue B

Block diagram updatedFigure 1.1All revisions
Introductory description updatedAbout the Cortex-M7 processor and core peripheralsAll revisions
Processor core registers diagram updatedCore registers All revisions
Thumb state description updatedThumb stateAll revisions
Program Counter description updatedProgram CounterAll revisions
Base Priority Mask Register description updatedBase Priority Mask RegisterAll revisions
Second Note updatedException entryAll revisions
ASR #3 diagram updatedFigure 3.1All revisions
Operation section updatedCLREXAll revisions
CPUID reset value updatedTable 4.12r1p1
Updated ACTLR.DISCRITAXIRUW bit description Auxiliary Control RegisterAll revisions
CPUID.Variant and CPUID.Revisionfunctions updatedTable 4.14r1p1
AIRCR.SYSRESETREQ function updatedTable 4.17All revisions
Cache maintenance operations introduction updatedCache maintenance operationsAll revisions
More CMSIS access cache maintenance operations addedTable 4.67r1p1
Invalidate the entire data cache updated Initializing and enabling the L1 cacheAll revisions
CACR.SIWT function updatedL1 Cache Control RegisterAll revisions
Code example updatedDisabling cache error checking and correctionAll revisions
Two Glossary terms addedGlossaryAll revisions

Table B.3. Differences between issue B and issue C

Memory system ordering of memory accesses updatedMemory system ordering of memory accessesAll revisions
CPUID reset value updatedTable 4.12r1p2

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