4.3.8. System Handler Priority Registers

The SHPR1-SHPR3 registers set the priority level of the exception handlers. The maximum range of configurable priority values is 0-255. The actual range of priority values available is implementation defined.

SHPR1-SHPR3 are byte accessible. See the register summary in Table 4.12 for their attributes.

The system fault handlers, priority fields and registers are identified in Table 4.21.

Table 4.21. System fault handler priority fields

HandlerFieldRegister description
MemManagePRI_4System Handler Priority Register 1
BusFaultPRI_5
UsageFaultPRI_6
SVCallPRI_11System Handler Priority Register 2
PendSVPRI_14System Handler Priority Register 2
SysTickPRI_15

Each PRI_n field can be up to 8 bits wide, but the processor implements only bits[7:M] of each field, where M is implementation defined. Bits[M-1:0] read as zero and ignore writes.

System Handler Priority Register 1

The bit assignments are:

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Table 4.22. SHPR1 register bit assignments

BitsNameFunction
[31:24]PRI_7Reserved
[23:16]PRI_6Priority of system handler 6, UsageFault
[15:8]PRI_5Priority of system handler 5, BusFault
[7:0]PRI_4Priority of system handler 4, MemManage

System Handler Priority Register 2

The bit assignments are:

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Table 4.23. SHPR2 register bit assignments

BitsNameFunction
[31:24]PRI_11Priority of system handler 11, SVCall
[23:0]-Reserved

System Handler Priority Register 3

The bit assignments are:

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Table 4.24. SHPR3 register bit assignments

BitsNameFunction
[31:24]PRI_15Priority of system handler 15, SysTick exception
[23:16]PRI_14Priority of system handler 14, PendSV
[15:0]-Reserved

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