2.2.3. Behavior of memory accesses

The behavior of accesses to each region in the memory map is:

Table 2.11. Memory access behavior

Address rangeMemory regionMemory type[a]XN[a]Description

0x00000000- 0x1FFFFFFF

Code

Normal 

-Executable region for program code. You can also put data here.

0x20000000- 0x3FFFFFFF

SRAM

Normal 

-

Executable region for data. You can also put code here.

0x40000000- 0x5FFFFFFF

Peripheral

Device 

XNPeripheral address space.

0x60000000- 0x9FFFFFFF

External RAM

Normal 

-Executable region for data. You can also put code here.

0xA0000000- 0xDFFFFFFF

External device 

Device 

XNExternal Device memory.

0xE0000000- 0xE00FFFFF

Private Peripheral Bus

Strongly Ordered 

XN 

This region includes the NVIC, System timer, and system control block.

0xE0100000- 0xFFFFFFFF

Vendor-specific device

Device 

XN 

Accesses to this region are to vendor-specific peripherals.

[a] See Memory regions, types and attributes for more information.


The Code, SRAM, and external RAM regions can hold programs.

The optional MPU can override the default memory access behavior described in this section. For more information, see Optional Memory Protection Unit.

Additional memory access constraints for caches and shared memory

When a system includes caches or shared memory, some memory regions have additional access constraints, and some regions are subdivided, as Table 2.12 shows:

Table 2.12. Memory region shareability and cache policies

Address rangeMemory regionMemory typeShareabilityCache policy

0x00000000-0x1FFFFFFF

Code

Normal [a]

Non-shareable [a]WT [b]

0x20000000-0x3FFFFFFF

SRAM

Normal [a]

Non-shareable [a]WBWA [b]

0x40000000-0x5FFFFFFF

Peripheral 

Device [a]

Non-shareable [a]-

0x60000000-0x7FFFFFFF

External RAM

Normal [a]

Non-shareable [a]WBWA [b]

0x80000000-0x9FFFFFFF

WT [b]

0xA0000000-0xBFFFFFFF

External device 

Device [a]

Shareable [a]-
0xC0000000-0xDFFFFFFFNon-shareable [a]

0xE0000000-0xE00FFFFF

Private Peripheral Bus

Strongly Ordered [a]

Shareable [a]-

0xE0100000-0xFFFFFFFF

Vendor-specific device 

Device [a]

Non-shareable[a] -

[a] See Memory regions, types and attributes for more information.

[b] WT = Write through, no Write Allocate. WBWA = Write Back, Write Allocate.


Instruction prefetch and branch prediction

The Cortex-M7 processor:

  • Prefetches instructions ahead of execution.

  • Speculatively prefetches from branch target addresses.

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