3.8.2. SXT and UXT

Sign extend and Zero extend.

Syntax

op{cond} Rd, Rn {, ROR #n}         ; SXTB; SXTH; UXTB; UXTH
op{cond} {Rd}, Rn {, ROR #n}       ; SXTB16; UXTB16

Where:

op

Is one of:

SXTB

Sign extends an 8‑bit value to a 32‑bit value.

SXTH

Sign extends a 16‑bit value to a 32‑bit value.

SXTB16

Sign extends two 8-bit values to two 16-bit values.

UXTB

Zero extends an 8‑bit value to a 32‑bit value.

UXTH

Zero extends a 16‑bit value to a 32‑bit value.

UXTB16

Zero extends two 8-bit values to two 16-bit values.

cond

Is an optional condition code. See Conditional execution.

Rd

Is the destination register. If Rd is omitted, the destination register is Rn.

Rn

Is the register holding the value to extend.

ROR #n

Is one of:

ROR #8

Value from Rm is rotated right 8 bits.

ROR #16

Value from Rm is rotated right 16 bits.

ROR #24

Value from Rm is rotated right 24 bits.

If ROR #n is omitted, no rotation is performed.

Operation

These instructions do the following:

  1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.

  2. Extract bits from the resulting value:

    • SXTB extracts bits[7:0] and sign extends to 32 bits.

    • UXTB extracts bits[7:0] and zero extends to 32 bits.

    • SXTH extracts bits[15:0] and sign extends to 32 bits.

    • UXTH extracts bits[15:0] and zero extends to 32 bits.

    • SXTB16 extracts bits[7:0] and sign extends to 16 bits, and extracts bits [23:16] and sign extends to 16 bits.

    • UXTB16 extracts bits[7:0] and zero extends to 16 bits, and extracts bits [23:16] and zero extends to 16 bits.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the flags.

Examples

SXTH  R4, R6, ROR #16  ; Rotates R6 right by 16 bits, obtains bottom halfword of
                       ; of result, sign extends to 32 bits and writes to R4
UXTB  R3, R10          ; Extracts lowest byte of value in R10, zero extends, and
                       ; writes to R3.
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