4.1. About the Cortex-M7 peripherals

The address map of the Private peripheral bus (PPB) is:

Table 4.1. Core peripheral register regions

AddressCore peripheralDescription
0xE000E008-0xE000E00FSystem control blockTable 4.12
0xE000E010-0xE000E01FSystem timerTable 4.33
0xE000E100-0xE000E4EFNested Vectored Interrupt ControllerTable 4.2
0xE000ED00-0xE000ED3FSystem control blockTable 4.12
0xE000ED78-0xE000ED84Processor features[a]Table 4.39
0xE000ED90-0xE000EDB8Memory Protection Unit[a][b]Table 4.48
0xE000EF00-0xE000EF03Nested Vectored Interrupt ControllerTable 4.2
0xE000EF30-0xE000EF44Floating Point Unit[a]Table 4.58
0xE000EF50-0xE000EF78Cache maintenance operations[a]Table 4.64

0xE000EF90-0xE000EFA8

Access control[a]Table 4.68

[a] This core peripheral is an optional implementation.

[b] Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a Memory Protection Unit (MPU).


In register descriptions:

Note

Attempting to access a privileged register from unprivileged software results in a BusFault.

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