4.2. Nested Vectored Interrupt Controller

This section describes the NVIC and the registers it uses. The NVIC supports:

The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. The hardware implementation of the NVIC registers is:

Table 4.2. NVIC register summary

Address[a]Name[b]Type

Required

privilege

Reset

value

Description
0xE000E100- 0xE000E11CNVIC_ISER0- NVIC_ISER7RWPrivileged0x00000000Interrupt Set-enable Registers
0XE000E180- 0xE000E19CNVIC_ICER0- NVIC_ICER7RWPrivileged0x00000000Interrupt Clear-enable Registers
0XE000E200- 0xE000E21CNVIC_ISPR0- NVIC_ISPR7RWPrivileged0x00000000Interrupt Set-pending Registers
0XE000E280- 0xE000E29CNVIC_ICPR0- NVIC_ICPR7RWPrivileged0x00000000Interrupt Clear-pending Registers
0xE000E300- 0xE000E31CNVIC_IABR0- NVIC_IABR7RWPrivileged0x00000000Interrupt Active Bit Registers
0xE000E400- 0xE000E4EFNVIC_IPR0- NVIC_IPR59RWPrivileged0x00000000Interrupt Priority Registers
0xE000EF00STIRWOConfigurable[c]0x00000000Software Trigger Interrupt Register

[a] The address ranges are implementation defined.

[b] The range of registers is implementation defined.

[c] See the register description for more information.


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