4.2.2. Interrupt Set-enable Registers

The NVIC_ISER0-NVIC_ISER7 registers enable interrupts, and show which interrupts are enabled. See the register summary in Table 4.2 for the register attributes.

The bit assignments are:

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Table 4.4. ISER bit assignments

BitsNameFunction
[31:0]SETENA

Interrupt set-enable bits.

Write:

0

No effect.

1

Enable interrupt.

Read:

0

Interrupt disabled.

1

Interrupt enabled.


If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.

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