4.3.10. Configurable Fault Status Register

The CFSR indicates the cause of a MemManage fault, BusFault, or UsageFault. See the register summary in Table 4.12 for its attributes. The bit assignments are:

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The following subsections describe the subregisters that make up the CFSR:

The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:

MemManage Fault Status Register

The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are:

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Table 4.26. MMFSR bit assignments

BitsNameFunction
[7]MMARVALID

MemManage Fault Address Register (MMFAR) valid flag:

0

Value in MMAR is not a valid fault address.

1

MMAR holds a valid fault address.

If a MemManage fault occurs and is escalated to a HardFault because of priority, the HardFault handler must set this bit to 0. This prevents problems on return to a stacked active MemManage fault handler whose MMAR value has been overwritten.

[6]-Reserved.
[5]MLSPERR[a]
0

No MemManage fault occurred during floating-point lazy state preservation.

1

A MemManage fault occurred during floating-point lazy state preservation.

[4]MSTKERR

MemManage fault on stacking for exception entry:

0

No stacking fault.

1

Stacking for an exception entry has caused one or more access violations.

When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor has not written a fault address to the MMAR.

[3]MUNSTKERR

MemManage fault on unstacking for a return from exception:

0

No unstacking fault.

1

Unstack for an exception return has caused one or more access violations.

This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The processor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a fault address to the MMAR.

[2]-Reserved.
[1]DACCVIOL

Data access violation flag:

0

No data access violation fault.

1

The processor attempted a load or store at a location that does not permit the operation.

When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has loaded the MMAR with the address of the attempted access.

[0]IACCVIOL

Instruction access violation flag:

0

No instruction access violation fault.

1

The processor attempted an instruction fetch from a location that does not permit execution.

This fault occurs on any access to an XN region, even when the MPU is disabled or not present.

When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not written a fault address to the MMAR.

[a] This field is optional and might not be available in your implementation.


Note

The MMFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.

BusFault Status Register

The flags in the BFSR indicate the cause of a bus access fault. The bit assignments are:

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Table 4.27. BFSR bit assignments

BitsNameFunction
[7]BFARVALID

BusFault Address Register (BFAR) valid flag:

0

Value in BFAR is not a valid fault address.

1

BFAR holds a valid fault address.

The processor sets this bit to 1 after a BusFault where the address is known. Other faults can set this bit to 0, such as a MemManage fault occurring later.

If a BusFault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents problems if returning to a stacked active BusFault handler whose BFAR value has been overwritten.

[6]-Reserved.
[5]LSPERR[a]
0

No bus fault occurred during floating-point lazy state preservation.

1

A bus fault occurred during floating-point lazy state preservation.

[4]STKERR

BusFault on stacking for exception entry:

0

No stacking fault.

1

Stacking for an exception entry has caused one or more BusFaults.

When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the BFAR.

[3]UNSTKERR

BusFault on unstacking for a return from exception:

0

No unstacking fault.

1

Unstack for an exception return has caused one or more BusFaults.

This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write a fault address to the BFAR.

[2]IMPRECISERR

Imprecise data bus error:

0

No imprecise data bus error.

1

A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error.

When the processor sets this bit to 1, it does not write a fault address to the BFAR.

This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the BusFault priority, the BusFault becomes pending and becomes active only when the processor returns from all higher priority processes. If a precise fault occurs before the processor enters the handler for the imprecise BusFault, the handler detects both IMPRECISERR set to 1 and one of the precise fault status bits set to 1.

[1]PRECISERR

Precise data bus error:

0

No precise data bus error.

1

A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault.

When the processor sets this bit to 1, it writes the faulting address to the BFAR.

[0]IBUSERR

Instruction bus error:

0

No instruction bus error.

1

Instruction bus error.

The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it attempts to issue the faulting instruction.

When the processor sets this bit to 1, it does not write a fault address to the BFAR.

[a] This field is optional and might not be available in your implementation.


Note

The BFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.

UsageFault Status Register

The UFSR indicates the cause of a UsageFault. The bit assignments are:

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Table 4.28. UFSR bit assignments

BitsNameFunction
[15:10]-Reserved.
[9]DIVBYZERO

Divide by zero UsageFault:

0

No divide by zero fault, or divide by zero trapping not enabled.

1

The processor has executed an SDIV or UDIV instruction with a divisor of 0.

When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the divide by zero.

Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see Configuration and Control Register.

[8]UNALIGNED

Unaligned access UsageFault:

0

No unaligned access fault, or unaligned access trapping not enabled.

1

The processor has made an unaligned memory access.

Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the CCR to 1, see Configuration and Control Register.

Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP.

[7:4]-Reserved.
[3]NOCP

No coprocessor UsageFault:

0

No UsageFault caused by attempting to access a coprocessor.

1

The processor has attempted to access a coprocessor.

The processor does not support coprocessor instructions.

[2]INVPC

Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN:

0

No invalid PC load UsageFault.

1

The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value.

When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC.

[1]INVSTATE

Invalid state UsageFault:

0

No invalid state UsageFault.

1

The processor has attempted to execute an instruction that makes illegal use of the EPSR.

When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR.

This bit is not set to 1 if an undefined instruction uses the EPSR.

[0]UNDEFINSTR

Undefined instruction UsageFault:

0

No undefined instruction UsageFault.

1

The processor has attempted to execute an undefined instruction.

When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction.

An undefined instruction is an instruction that the processor cannot decode.


Note

The UFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.

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