4.3.3. Interrupt Control and State Register

The ICSR:

See the register summary in Table 4.12, and the Type descriptions in Table 4.15, for the ICSR attributes. The bit assignments are:

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Table 4.15. ICSR bit assignments

BitsNameTypeFunction
[31]NMIPENDSETRW

NMI set-pending bit.

Write:

0

No effect.

1

Changes NMI exception state to pending.

Read:

0

NMI exception is not pending.

1

NMI exception is pending.

Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers a write of 1 to this bit, and entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.

[30:29]--Reserved.
[28]PENDSVSETRW

PendSV set-pending bit.

Write:

0

No effect.

1

Changes PendSV exception state to pending.

Read:

0

PendSV exception is not pending.

1

PendSV exception is pending.

Writing 1 to this bit is the only way to set the PendSV exception state to pending.

[27]PENDSVCLRWO

PendSV clear-pending bit.

Write:

0

No effect.

1

Removes the pending state from the PendSV exception.

[26]PENDSTSETRW

SysTick exception set-pending bit.

Write:

0

No effect.

1

Changes SysTick exception state to pending.

Read:

0

SysTick exception is not pending.

1

SysTick exception is pending.

[25]PENDSTCLRWO

SysTick exception clear-pending bit.

Write:

0

No effect.

1

Removes the pending state from the SysTick exception.

This bit is WO. On a register read its value is Unknown.

[24]--Reserved.
[23]Reserved for Debug useROThis bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
[22]ISRPENDINGRO

Interrupt pending flag, excluding NMI and Faults:

0

Interrupt not pending.

1

Interrupt pending.

[21]--Reserved.
[20:12]VECTPENDINGRO

Indicates the exception number of the highest priority pending enabled exception:

0

No pending exceptions.

Nonzero

The exception number of the highest priority pending enabled exception.

The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.

[11]

RETTOBASE

RO

Indicates whether there are preempted active exceptions:

0

There are preempted active exceptions to execute.

1

There are no active exceptions, or the currently-executing exception is the only active exception.

[10:9]--Reserved.
[8:0]VECTACTIVE[a]RO

Contains the active exception number:

0

Thread mode.

1

The exception number[a] of the currently active exception.

Note

Subtract 16 from this value to obtain the CMSIS IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending, or Priority Registers, see Table 2.5.

[a] This is the same value as IPSR bits[8:0], see Interrupt Program Status Register.


When you write to the ICSR, the effect is unpredictable if you:

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