4.2.7. Interrupt Priority Registers

The NVIC_IPR0-NVIC_IPR59 registers provide a priority field for each interrupt. These registers are byte-accessible. See the register summary in Table 4.2 for their attributes. Each register holds four priority fields as shown:

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Table 4.9. IPR bit assignments

[31:24]Priority, byte offset 3

Each priority field holds a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. If enabled, the processor can implement only bits[7:n] of each field, bits[n-x:0] read as zero and ignore writes. The values of n and x are implementation defined.

[23:16]Priority, byte offset 2
[15:8]Priority, byte offset 1
[7:0]Priority, byte offset 0

See Accessing the Cortex-M7 NVIC registers using CMSIS for more information about the access to the interrupt priority array, that provides the software view of the interrupt priorities.

Find the IPR number and byte offset for interrupt m as follows:

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