4.3.6. System Control Register

The SCR controls features of entry to and exit from low power state. See the register summary in Table 4.12 for its attributes. The bit assignments are:

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 4.19. SCR bit assignments


Send Event on Pending bit:


Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.


Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.

The processor also wakes up on execution of an SEV instruction or an external event.


Controls whether the processor uses sleep or deep sleep as its low power mode:




Deep sleep.


Indicates sleep-on-exit when returning from Handler mode to Thread mode:


Do not sleep when returning to Thread mode.


Enter sleep, or deep sleep, on return from an ISR.

Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.


Copyright © 2015, 2018 Arm. All rights reserved.ARM DUI 0646C