4.2.4. Interrupt Set-pending Registers

The NVIC_ISPR0-NVIC_ISPR7 registers force interrupts into the pending state, and show which interrupts are pending. See the register summary in Table 4.2 for the register attributes.

The bit assignments are:

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Table 4.6. ISPR bit assignments

BitsNameFunction
[31:0]SETPEND

Interrupt set-pending bits.

Write:

0

No effect.

1

Changes interrupt state to pending.

Read:

0

Interrupt is not pending.

1

Interrupt is pending.


Note

Writing 1 to the ISPR bit corresponding to:

  • An interrupt that is pending has no effect.

  • A disabled interrupt sets the state of that interrupt to pending.

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