2.4.1. Fault types

Table 2.16 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred. See Configuration and Control Register for more information about the fault status registers.

Table 2.16. Faults

FaultHandlerBit nameFault status register
Bus error on a vector readHardFaultVECTTBLHardFault Status Register
Fault escalated to a hard faultFORCED
MPU or default memory map mismatch:MemManage--
 On instruction accessIACCVIOL [a]MemManage Fault Status Register
 On data access[b]DACCVIOL
 During exception stacking[b]MSTKERR
 During exception unstacking[b]MUNSKERR
 During lazy floating-point state preservation[c]MLSPERR
Bus error:BusFault --
 During exception stackingSTKERRBusFault Status Register
 During exception unstackingUNSTKERR
 During instruction prefetchIBUSERR
 During lazy floating-point state preservation[d]LSPERR
Precise data bus errorPRECISERR
Imprecise data bus errorIMPRECISERR
Attempt to access a coprocessorUsageFaultNOCPUsageFault Status Register
Undefined instructionUNDEFINSTR
Attempt to enter an invalid instruction set state [e]INVSTATE
Illegal unaligned load or storeUNALIGNED

[a] Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.

[b] Occurs only if an MPU is implemented and enabled.

[c] Occurs only if an MPU and FPU are implemented and enabled.

[d] Occurs only if an FPU is implemented and enabled.

[e] Attempting to use an instruction set other than the Thumb instruction set or returns to a non load/store-multiple instruction with ICI continuation.

Copyright © 2015, 2018 Arm. All rights reserved.ARM DUI 0646C